Complementary Duty Cycle Correction Circuits for PVT Stability
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Solution Overview
Problem
Conventional duty cycle correction circuits fail to maintain a 50% duty cycle across a wide range of process, voltage, and temperature variations, leading to duty cycle distortion and data transmission errors in DDR systems.
Innovation Solution
The implementation of a duty cycle correction circuit with four inverters, each having variable pull-up and pull-down resistances that are symmetrically tuned to maintain a stable duty cycle, reducing distortion across various corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty cycle correction circuits are used, then duty cycle correction is provided, but duty cycle distortion occurs across process, voltage, and temperature variations
Solution Approach 1:
The patent applies asymmetry by using different inverter configurations for rising and falling edges. Specifically, the first inverter has a first pull-up transistor and first pull-down transistor with different sizing ratios than the second inverter's pull-up and pull-down transistors. This asymmetric design allows independent optimization of rising and falling edge characteristics, enabling the circuit to compensate for PVT variations that affect each edge differently, thereby maintaining stable 50% duty cycle across process, voltage, and temperature corners.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the effective resistance of pull-up and pull-down networks through transistor switching. The circuit includes control logic that monitors duty cycle deviations and switches between different transistor combinations (e.g., changing which of multiple pull-up transistors are active) to modify the charging and discharging rates of the clock signal. This dynamic parameter adjustment allows the circuit to adapt to PVT variations and maintain accurate duty cycle correction.
2Device complexity
If single inverter configuration is used, then circuit simplicity is maintained, but rising and falling edges cannot be independently optimized
Solution Approach 1:
The patent applies segmentation by dividing the duty cycle correction function into two independent inverter stages: a first inverter for correcting the rising edge and a second inverter for correcting the falling edge. Each inverter has its own independently sized pull-up and pull-down transistors, allowing separate optimization of rising and falling edge characteristics. This segmentation enables precise control over each edge's timing without interference from the other, achieving high duty cycle accuracy while maintaining reasonable circuit complexity through modular design.
Data Source
AI summary
Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.