Duty Cycle Correction Circuit Without Large RC Filters

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Solution Overview

Problem

Conventional duty cycle correcting circuits require large RC circuits to achieve accurate correction, especially at low frequencies, which occupy significant space.

Innovation Solution

A duty cycle correcting circuit that uses a duty adjustor circuit, charge pumps, sampling and hold circuits, and an error amplifier to adjust the duty cycle without relying on a large RC circuit, by generating tuning signals based on the difference between sampled voltages from first and second capacitors charged for predetermined and duty cycle-corresponding time periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a low pass filter with resistors and capacitors is used to acquire DC voltage for duty cycle correction, then the correction accuracy can be achieved, but the circuit area becomes large when the output clock frequency is low

Engineering Contradiction:
Improveduty cycle correction accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent replaces the conventional RC low pass filter (analog circuit) with a charge pump circuit combined with sampling and hold circuits (digital-like circuit). The charge pump charges capacitors during specific time periods to generate voltages that are then sampled and compared, eliminating the need for large RC components while achieving the same duty cycle correction function.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operating parameters by using switched-capacitor techniques where capacitors are charged for specific time periods (full period and duty cycle period) to generate proportional voltages. This time-based charging approach replaces the frequency-dependent RC filtering, allowing accurate duty cycle measurement without large physical components.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the output clock frequency is low, then the duty cycle correction accuracy requirement increases, but the RC circuit area must be larger to meet this requirement

Engineering Contradiction:
Improveduty cycle correction accuracyVSAvoidRC circuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent substitutes the frequency-dependent RC low pass filter with a charge pump and sampling system that operates independently of output clock frequency. The charge pump generates voltages based on time-period charging, and the sampling and comparison process extracts duty cycle information without requiring large RC time constants, thus maintaining accuracy across different frequencies without increasing area.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables duty cycle adjustment without the need for large RC circuits, allowing for compact design and accurate duty cycle correction across various frequencies.

Implementation Method 1

a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12143109B1Device for correcting duty cycle and method for correcting duty cycle
Publication Date: 2024.11.12 MEDIATEK SINGAPORE PTE LTD
  • US12143109B1 patent drawing
  • US12143109B1 patent drawing
  • US12143109B1 patent drawing

AI summary

A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.