Duty Cycle Correction Circuit Using Phase-Shifted Reset Pulses
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Solution Overview
Problem
High-speed quadrature clock systems face challenges in maintaining a 50% duty cycle due to limitations in existing methods, which are either impractical at high frequencies, inefficient in power consumption, or have limited correction ranges, and are sensitive to Process, Voltage, and Temperature (PVT) variations.
Innovation Solution
A clock duty cycle correction circuit using two clocks with opposite phases, where one is phase-shifted and delayed to generate a reset signal that adjusts the original clock signal to achieve a symmetrical output with approximately 50% duty cycle, without altering the clock rate or significantly increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the clock rate is doubled before dividing by 2 to achieve 50% duty cycle, then the duty cycle accuracy is improved, but the system becomes infeasible at high frequencies (5 GHz and above) and the system clock speed is reduced
Solution Approach 1:
The patent segments the duty cycle correction function into two independent paths: one path processes the original clock signal while the other processes a phase-shifted version of the same clock signal. By operating on segmented versions of the clock signal rather than doubling the frequency, the circuit achieves duty cycle correction without increasing the system clock rate or reducing operational speed.
Solution Approach 2:
The patent introduces a phase-shifted clock signal as an intermediary element to generate the reset signal. This intermediary signal, which is phase-shifted by approximately 180 degrees, enables the duty cycle correction mechanism to function without requiring frequency multiplication, thereby maintaining system clock speed while achieving accurate 50% duty cycle output.
2Manufacturing precision
If positive feedback inverters are coupled to opposite phase clocks to correct duty cycle, then the duty cycle correction is achieved, but the power consumption increases significantly
Solution Approach 1:
The patent changes the operational parameters of the correction circuit by using phase-shifted clock signals to generate reset signals instead of using continuous positive feedback through inverters. This parameter change allows duty cycle correction to be achieved during specific phases of the clock cycle rather than continuously, significantly reducing power consumption while maintaining correction effectiveness.
Solution Approach 2:
The patent implements periodic action by using the phase-shifted clock signal to generate reset pulses only during specific intervals of the clock cycle. This periodic reset mechanism corrects duty cycle deviations without requiring continuous inverter operation, thereby reducing power consumption compared to continuous positive feedback approaches.
3Manufacturing precision
If conventional duty cycle correction methods are used, then some correction is achieved, but the correction range is limited and cannot handle severe duty cycle offsets
Solution Approach 1:
The patent applies preliminary action by generating the phase-shifted clock signal in advance and using it to create reset signals that proactively correct duty cycle deviations. This preliminary preparation of the phase-shifted signal enables the circuit to handle severe duty cycle offsets effectively, as the reset mechanism is ready to act regardless of the magnitude of the deviation from 50% duty cycle.
Solution Approach 2:
The patent employs asymmetry by using a phase-shifted version of the clock signal (approximately 180 degrees out of phase) rather than a symmetric or in-phase signal to generate the reset pulse. This asymmetric approach allows the reset signal to effectively counteract severe duty cycle deviations in either direction, expanding the correction range beyond what symmetric correction methods can achieve.
Data Source
AI summary
Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.