Duty Cycle Correction Circuit With Selective Delay and Phase Mixing
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Solution Overview
Problem
Conventional duty cycle correction circuits in semiconductor integrated circuits face challenges in precisely correcting the duty cycle of clock signals due to noise and high power consumption, which affects operation efficiency.
Innovation Solution
A circuit and method that includes a duty ratio digital conversion block, a duty ratio information analyzing block, and a duty ratio control block to generate edge control signals and select delayed clock signals, allowing for precise control of duty ratios and phase mixing to generate an output clock signal with a 50:50 duty ratio, reducing power consumption by enabling only necessary unit delays based on the duration ratio of the input clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional duty cycle correction circuits are used, then duty cycle correction is provided, but power consumption is high and correction precision is insufficient
Solution Approach 1:
The patent implements dynamic adjustment of the number of enabled unit delays based on the measured duration ratio of the input clock signal. The controller selectively enables or disables unit delays to match the actual duty cycle deviation, rather than using a fixed number of delays. This dynamic adaptation reduces power consumption while maintaining correction precision across varying input conditions.
Solution Approach 2:
The patent changes the operational parameters of the delay circuit by adjusting the number of enabled unit delays according to the measured duty cycle deviation. The controller modifies the enable signals to unit delays based on the duration ratio, thereby optimizing the correction amount and reducing power consumption without sacrificing correction accuracy.
2Adaptability or versatility
If all unit delays are enabled to cover all possible duty cycle deviations, then correction coverage is maximized, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the number of enabled unit delays based on the measured duration ratio of the input clock signal. Rather than statically enabling all unit delays to cover the full range of possible deviations, the controller enables only the necessary number of unit delays corresponding to the actual deviation magnitude, thereby maintaining full adaptability while reducing power consumption.
Solution Approach 2:
The patent applies partial action by enabling only the necessary subset of unit delays required to correct the measured duty cycle deviation, rather than enabling all unit delays. The controller determines the minimum number of unit delays needed based on the duration ratio and enables only those, avoiding the excessive power consumption that would result from enabling all unit delays regardless of actual needs.
3Productivity
If digital converter types and phase mixer types are used, then duty cycle correction is achieved, but correction ability and power efficiency are insufficient for high performance operation
Solution Approach 1:
The patent segments the duty cycle correction function into distinct modules: a duration ratio measurement unit that measures the input clock signal characteristics, a controller that determines the appropriate correction amount, and a delay circuit with multiple selectable unit delays that applies the correction. This segmented architecture improves operation efficiency by enabling precise, targeted correction while reducing power consumption compared to conventional digital converter or phase mixer approaches.
Solution Approach 2:
The patent replaces the conventional digital converter type or phase mixer type duty cycle correction mechanisms with a measurement-and-adjustment approach using duration ratio detection and selective delay enabling. This substitution achieves superior correction ability and power efficiency by directly measuring the actual duty cycle deviation and applying only the necessary correction through selectively enabled unit delays, rather than using complex digital conversion or phase mixing circuits.
Data Source
AI summary
A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.