Duty Cycle Correction Circuit Using Input and Delayed Signal Transitions
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Solution Overview
Problem
Conventional duty cycle correction (DCC) circuits in integrated circuit memory devices are limited by susceptibility to process, voltage, and temperature variations, and have a large intrinsic delay, restricting the duty ratios they can generate and affecting accuracy, especially when clock signals deviate significantly from a 50%:50% duty cycle.
Innovation Solution
A DCC circuit that maintains a duty cycle corrected signal by generating transitions responsive to input and delayed versions of the input signal, using a latch and transition generator circuit, along with a delay control unit and adjustable delay line, to accurately adjust the duty cycle based on phase differences, allowing for flexible generation of various duty ratios, including 50%:50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DCC circuits are used, then duty cycle correction is provided, but the circuits suffer from large intrinsic delay and susceptibility to process, voltage, and temperature variations
Solution Approach 1:
The DCC circuit is divided into multiple independent components: a phase detector that measures phase difference, a duty cycle generator that creates correction signals based on the measured phase difference, and a signal combiner that merges the correction signal with the input clock. This segmentation allows each component to be optimized independently, reducing overall intrinsic delay while maintaining correction accuracy.
Solution Approach 2:
The patent replaces conventional analog DCC mechanisms with a digital-based approach using phase detection and digital signal processing. The phase detector uses digital logic to measure phase difference, and the duty cycle generator uses digital counters and logic circuits to generate correction signals, eliminating the large intrinsic delays associated with analog correction circuits.
2Reliability
If conventional DCC circuits are used, then duty cycle correction is provided, but the control hardware is complex
Solution Approach 1:
The phase detector is designed to serve multiple functions: it detects phase difference between clocks, generates control signals for the duty cycle generator, and provides timing references for the overall circuit. This multi-functionality reduces the need for separate dedicated circuits, thereby simplifying the overall control hardware while maintaining correction accuracy.
Solution Approach 2:
The duty cycle generator automatically adjusts the correction signal based on the phase difference measurement without requiring external control logic. The circuit self-regulates by using the phase detector's output to directly control the correction signal generation, eliminating the need for complex external control hardware.
3Adaptability or versatility
If conventional DCC circuits are used, then duty cycle correction is provided, but flexibility in generating various duty ratios is limited
Solution Approach 1:
The duty cycle generator is designed with dynamic control capability, allowing the duty ratio to be adjusted based on the measured phase difference. The circuit can generate any duty ratio from 0% to 100% by varying the control signal width, providing full flexibility while maintaining precision through the phase-based control mechanism.
Solution Approach 2:
The patent changes the control parameter from fixed duty cycle to variable duty cycle based on phase difference measurement. By using the phase difference as the control parameter, the system can accurately generate any desired duty ratio, including cases where the input clock deviates significantly from 50%:50%, thereby improving both flexibility and measurement precision.
Data Source
AI summary
A duty cycle correction circuit is operated by maintaining a state of a duty cycle corrected signal, generating a first transition in the state of the duty cycle corrected signal responsive to an input signal, and generating a second transition in the state of the duty cycle corrected signal responsive to a delayed version of the input signal.


