Dual-Cycle Duty Detection Circuit for Stable Clock Duty Correction
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Solution Overview
Problem
The use of fixed-cycle duty determining circuits in DDR-SDRAMs leads to amplified variations in output clock duty ratios due to jitter fluctuations, as the duty correction condition is not frequently updated during the DLL locking period, resulting in unstable operation.
Innovation Solution
A semiconductor device employing both a fixed-cycle and a continuous duty determining circuit, where the fixed-cycle circuit updates the duty correction condition during the DLL locking period and the continuous circuit updates it only when the determination results are fixed, effectively suppressing jitter amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed-cycle duty determining circuit is used to update the duty correction condition in a predetermined cycle, then the circuit structure is simple, but the output clock duty ratio exhibits amplified variations when input clocks have jitter fluctuating close to the duty determining cycle
Solution Approach 1:
The patent applies dynamics by making the duty determination cycle variable rather than fixed. The control circuit dynamically adjusts the cycle period based on the operating state of the DLL. During the locking period, the cycle is set to a first period (shorter), and after locking, it switches to a second period (longer). This dynamic adjustment allows frequent updates during critical locking phases to suppress jitter amplification, while reducing updates after locking to maintain stability, thereby resolving the contradiction between simple structure and reliable output.
2Measurement precision
If the duty correction condition is frequently updated during the DLL locking period, then the duty ratio accuracy is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent implements periodic action by using different update periods for different operational phases. During the DLL locking period, the duty correction condition is updated frequently with a first period to ensure accurate duty ratio correction. After the DLL locks, the update period switches to a longer second period. This phased periodic approach maintains high measurement precision when needed while avoiding continuous high-frequency updates that would increase power consumption and circuit complexity unnecessarily.
Solution Approach 2:
The patent changes the parameter of the duty determination cycle period based on the DLL operating state. The control circuit transitions the cycle period from a first period during locking to a second period after locking. This parameter change allows the system to achieve high duty ratio accuracy during the critical locking phase without incurring the continuous overhead of high-frequency updates, thus balancing precision requirements with circuit complexity and power consumption constraints.
3Use of energy by moving object
If a longer duty determining cycle is used to reduce power consumption, then the power efficiency is improved, but the duty correction cannot keep up with rapid jitter variations
Solution Approach 1:
The patent applies dynamics by making the duty determination cycle adaptive rather than static. During the DLL locking period when jitter variations are most critical, the cycle is set to a shorter first period to ensure responsive duty correction. After locking, when the system is more stable, the cycle extends to a longer second period to reduce power consumption. This dynamic cycle adjustment resolves the contradiction between power efficiency and correction responsiveness by matching the update frequency to the actual system state.
Solution Approach 2:
The patent performs preliminary action by using a shorter duty determination cycle during the DLL locking period before the system reaches its stable operating state. This preliminary frequent updating ensures that duty correction keeps up with rapid jitter variations during the critical initialization phase. Once locking is achieved, the system transitions to a longer cycle for normal operation, thereby achieving responsive correction when most needed while maintaining power efficiency during stable operation.
Data Source
AI summary
A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.