DVB-H Packet Error Correction with Recursive CRC and Dual-Mode RS
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Solution Overview
Problem
The DVB-H standard's error correction mechanisms, particularly the erasure-based FEC RS decoder, are inadequate in mobile TV receivers, leading to decoding failures and unsmooth video or glitches due to excessive erasures exceeding 64 bytes, which results in discarded data bursts.
Innovation Solution
A dual mode FEC RS decoder is implemented with recursive CRC/Reed-Solomon and FEC decoding processes, using a Berlekamp-Massey algorithm to correct errors and reduce erasure counts below 64 bytes, enhancing error detection and correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erasure-based FEC RS decoding is used in DVB-H standard, then error correction capability is limited to 64 bytes per row, but this results in decoding failures when erasures exceed 64 bytes, leading to discarded data bursts and unsmooth video
Solution Approach 1:
The patent segments the error correction process into multiple iterative passes. Each pass processes rows with erasure counts below the 64-byte threshold, gradually reducing erasures through CRC-based error identification and correction. This segmentation allows the system to handle cases where total erasures exceed 64 bytes by breaking down the problem into manageable subsets that can be corrected incrementally across multiple decoding iterations.
Solution Approach 2:
The patent implements periodic action through iterative decoding cycles. The system repeatedly applies CRC checks and FEC decoding in alternating passes, periodically re-evaluating and correcting errors until convergence or maximum iteration count. This periodic application of error detection and correction mechanisms enables the system to progressively reduce erasure counts below the 64-byte threshold even when initial erasure counts exceed this limit.
2Reliability
If multiple iterative CRC/FEC decoding processes are implemented, then error correction capability is improved, but computational complexity and processing time increase
Solution Approach 1:
The patent applies preliminary action by performing CRC checks before FEC decoding to pre-identify error locations. This preliminary error detection step marks suspected error positions before the more computationally intensive FEC decoding process begins, allowing the decoder to focus computational resources on correcting specifically identified errors rather than processing all data uniformly across multiple iterations.
Solution Approach 2:
The patent implements feedback mechanisms where CRC check results from each decoding pass feed into the next iteration's decoding process. The system uses feedback from previous decoding attempts to adjust error correction strategies, re-mark erasures based on updated CRC results, and refine correction approaches in subsequent passes, thereby improving efficiency and reducing overall computational complexity.
3Measurement precision
If erasures are marked based on CRC failure, then error locations are identified, but all bytes in the datagram are marked as erasures leading to excessive erasure counts
Solution Approach 1:
The patent applies local quality by differentiating error marking at the byte level rather than treating entire datagrams uniformly. Instead of marking all bytes as erasures when a CRC failure occurs, the system identifies and marks only specific byte positions suspected of containing errors based on CRC syndrome analysis. This localized error marking reduces the total number of erasures from potentially thousands to a manageable subset that can be corrected within the 64-byte per row threshold.
Solution Approach 2:
The patent changes the parameter of erasure marking from a binary all-or-nothing approach to a graded, position-specific approach. The system modifies how erasures are quantified and distributed across the datagram, using CRC syndrome information to assign erasure markers selectively to specific byte positions rather than uniformly across all bytes. This parameter change in error marking strategy dramatically reduces the total erasure count while maintaining accurate error location identification.
Data Source
AI summary
A system and method of using recursive cyclic redundancy check (CRC)+forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder+FEC to achieve better coding gain. The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme for implementing the recursive CRC/RS+FEC in very large scale integrated circuit chip (VLSI) hardware.