Host Processor Assisted DVB-H Receiver Re-Synchronization
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Solution Overview
Problem
DVB-H receivers face high power consumption due to the need for on-chip timers and phase locked loop circuits to remain active during sleep mode for re-synchronization, which increases average power usage.
Innovation Solution
A method that involves removing on-chip timers and internal state registers and utilizing a host processor to manage re-synchronization tasks, allowing the DVB-H receiver to power off between data bursts, using stored values to expedite re-synchronization processes such as AGC lock, mode detection, frequency offset estimation, and timing and carrier loop lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip timers and internal state registers are kept active during sleep mode for re-synchronization, then re-synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the timer function from the DVB-H receiver chip and relocates it to the host processor. The host processor maintains the timer and manages re-synchronization, allowing the receiver's on-chip timer and internal state registers to be powered off during sleep mode while re-synchronization accuracy is maintained through host processor intervention.
2Reliability
If receiver stays active longer to perform re-synchronization before next burst, then re-synchronization completeness is improved, but average power consumption increases
Solution Approach 1:
The host processor performs preliminary actions by pre-calculating and storing re-synchronization parameters and timer values before the receiver enters sleep mode. When the receiver wakes up, these pre-prepared values are immediately applied, enabling fast re-synchronization without requiring the receiver to stay active for extended periods.
3Use of energy by moving object
If on-chip timer and internal state registers are removed, then power consumption is reduced, but re-synchronization capability is worsened
Solution Approach 1:
The host processor acts as an intermediary that compensates for the removal of on-chip timers and internal state registers. The host processor maintains timer functionality and manages re-synchronization state externally, providing the necessary timing and state management capabilities without requiring these components to be present on the receiver chip.
Data Source
AI summary
A system and method of performing re-synchronization for a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein the method comprises performing a time division multiplexing (TDM) data burst transmission sequence on bits of data received by the DVB-H receiver; performing a data bit re-synchronization sequence on the DVB-H receiver; removing an on-chip timer and internal state registers in the DVB-H receiver; and allowing the DVB-H receiver to power off in between receipt of data bursts. Preferably, the removing process reduces the time to perform the re-synchronization in the DVB-H receiver. Preferably, the data bit re-synchronization sequence comprises performing an automatic gain control (AGC) lock process; performing a mode and guard detecting process; performing a frequency offset estimation process; performing a transmit parameter signaling (TPS) detection process; performing a timing and carrier loop lock process; and performing an equalizer delay process.