Quasi-Cyclic LDPC Matrix Layout for DVB-S2 Error Floor Reduction

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Solution Overview

Problem

DVB-S2 LDPC codes suffer from performance degradation due to high error floor phenomenon at high Signal to Noise Ratios (SNR) due to suboptimal cycle characteristics in their Tanner graphs, lacking effective methods to design LDPC codes with improved cycle characteristics.

Innovation Solution

A method for designing a parity-check matrix of a quasi-cyclic LDPC code based on circulant permutation matrices, optimizing the cycle characteristics of the Tanner graph by rearranging columns and rows, resulting in a DVB-S2 LDPC code with enhanced performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DVB-S2 LDPC codes are used for communication, then data throughput and reliability are improved, but error floor phenomenon occurs at high SNR due to suboptimal cycle characteristics in Tanner graphs

Engineering Contradiction:

Improvecommunication reliabilityVSAvoiderror floor phenomenon

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by modifying the structure of the parity-check matrix through column and row rearrangement operations. Specifically, it transforms the original DVB-S2 LDPC code's parity-check matrix into a new configuration that changes the cycle characteristics of the Tanner graph, thereby reducing the error floor phenomenon while maintaining the code's error correction capability at high SNR

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If standard DVB-S2 LDPC code structure is maintained, then implementation simplicity is preserved, but cycle characteristics in Tanner graphs are suboptimal leading to performance degradation

Engineering Contradiction:

Improveimplementation simplicityVSAvoidcode performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the parity-check matrix into information word columns and parity columns, and applies different transformation operations to each segment. The column rearrangement is performed in a structured manner that maintains the quasi-cyclic property while improving cycle characteristics, thus balancing implementation simplicity with enhanced performance

Inventive Principle:

Principle #1Segmentation

3Reliability

If column and row rearrangement is applied to optimize Tanner graph cycle characteristics, then error floor performance is improved, but code structure complexity increases

Engineering Contradiction:

Improveerror floor performanceVSAvoidcode structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces asymmetry in the parity-check matrix structure through selective column and row rearrangement. The transformation creates an asymmetric configuration that optimizes the Tanner graph's cycle characteristics by distributing cycles more uniformly, thereby improving error floor performance while the systematic approach keeps the complexity manageable

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentEP2091156B1Apparatus and method for channel encoding and decoding in a communication system using low-density parity-check codes

Publication Date: 2013.08.28 SAMSUNG ELECTRONICS CO LTD

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AI summary

An apparatus and method for generating a parity-check matrix of a Low-Density Parity-Check (LDPC) code are provided. Parameters for designing the LDPC code are determined, and a first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix, and a third parity-check matrix is created by rearranging the second parity-check matrix.