Partly Parallel LDPC Decoder Memory Architecture for DVB-S2
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Solution Overview
Problem
Existing LDPC decoder architectures face challenges with severe routing congestion and high area, power consumption due to the need for separate memories for variable and check nodes, leading to read/write conflicts and inefficiencies in memory usage, particularly in partly parallel architectures for irregular LDPC codes like DVB-S2.
Innovation Solution
A partly parallel LDPC decoder architecture with a shuffling network controlled by shift values, using single port memory partitions and a memory controller to manage message storage and updates, avoiding read/write conflicts and reducing memory size by using a hierarchy of memory banks and buffers, allowing efficient area reduction and power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separate memories are used for variable nodes and check nodes, then message storage capacity is improved, but memory area and power consumption increase
Solution Approach 1:
The patent merges separate memory structures for variable nodes and check nodes into a unified memory architecture. The same memory array is used to store messages for both node types by dynamically configuring memory addresses and access patterns based on whether variable node or check node processing is active, thereby reducing total memory area while maintaining full storage capacity.
Solution Approach 2:
The memory system is designed to serve multiple functions: it stores messages for variable nodes during variable processing phases, stores messages for check nodes during check processing phases, and provides read/write access patterns that adapt to the current operational mode. This multi-functional design eliminates the need for dedicated separate memories for each node type.
2Quantity of substance
If separate memories are used for variable nodes and check nodes, then message storage is improved, but power consumption increases
Solution Approach 1:
By combining memory resources into a single shared structure, the patent reduces the total number of memory devices that need to be powered and controlled. The unified memory system activates only the necessary storage locations for the current processing phase, reducing overall power consumption compared to maintaining separate always-active memory structures.
Solution Approach 2:
The memory system dynamically allocates and deallocates storage space for variable nodes and check nodes based on processing phase requirements. During variable processing, check node messages are discarded from active memory and recovered later during check processing phases, allowing the same physical memory to be reused and reducing sustained power requirements.
3Speed
If fully parallel architecture is used, then decoding speed is improved, but routing congestion increases
Solution Approach 1:
The patent segments the fully parallel architecture into phased processing stages: variable processing phases followed by check processing phases. This segmentation allows messages to be processed in organized batches rather than all simultaneously, reducing the peak routing load and congestion while maintaining high overall throughput through efficient phase transitions.
Solution Approach 2:
The decoder operates in periodic alternating phases between variable node processing and check node processing. This periodic action pattern allows the routing infrastructure to be reused in alternating time slots for different message types, reducing concurrent routing conflicts and congestion compared to fully simultaneous parallel processing of all node types.
4Reliability
If irregular LDPC codes are used, then error correction performance is improved, but memory access complexity increases
Solution Approach 1:
The patent implements dynamic memory access control that adapts to the irregular connectivity patterns of LDPC codes. The memory address generation and access timing are dynamically configured based on the specific variable and check node degrees, allowing the system to handle irregular code structures efficiently without requiring static complex routing infrastructure designed for regular codes.
Solution Approach 2:
The memory system changes its access parameters (addressing patterns, timing, data width) based on the current processing phase and the specific irregular LDPC code being decoded. This parameter adaptation allows the same memory hardware to efficiently support various irregular code structures with different node degrees and connectivity patterns without requiring dedicated complex memory architectures for each code type.
Data Source
AI summary
The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.