16K DVB Symbol Interleaver Using LFSR Address Permutation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing Digital Video Broadcasting (DVB) standards, such as DVB-T and DVB-H, face challenges in efficiently mapping data symbols onto the sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols, particularly in the 16k mode, which requires optimal interleaving to separate symbols and improve error correction coding performance amidst correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus with a symbol interleaver that utilizes a linear feedback shift register and permutation circuit to generate addresses for mapping data symbols onto OFDM sub-carrier signals, employing a specific generator polynomial and permutation order to achieve optimal interleaving, allowing for flexible implementation across different modes like 2k, 4k, 8k, and 16k, and enabling efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is used to interleave input data symbols onto sub-carrier signals of OFDM symbols, then the integrity of data communicated using DVB-T or DVB-H is improved, but the device complexity increases due to the need for interleaver memory and address generator
Solution Approach 1:
The patent applies parameter changes by modifying the address generation parameters (generator polynomial coefficients, permutation order) to optimize interleaving performance for different modes (2k, 8k, 16k). The address generator uses a linear feedback shift register with specific tap positions determined by generator polynomials, and the permutation circuit reorders addresses according to specific permutation orders. These parameter changes enable effective symbol separation to combat correlated fading while maintaining a consistent interleaver structure across different modes.
2Productivity
If the number of sub-carriers is increased from 2k to 8k mode to improve data communication capacity, then the productivity increases, but the difficulty of detecting and measuring increases due to more sub-carriers requiring addressing
Solution Approach 1:
The patent replaces a complex mechanical addressing system with a mathematical algorithm-based address generator. Instead of manually or mechanically assigning addresses to each sub-carrier, the system uses a linear feedback shift register governed by generator polynomials and a permutation circuit to automatically generate and reorder addresses. This substitution of mathematical algorithms for mechanical addressing simplifies the system while enabling scalability to higher modes (2k, 8k, 16k) with more sub-carriers.
3Adaptability or versatility
If a linear feedback shift register with permutation circuit is used to generate addresses for mapping, then the adaptability across different modes (2k, 8k, 16k) is improved, but the device complexity increases
Solution Approach 1:
The patent implements universality by designing a single address generator structure that can serve multiple modes (2k, 8k, 16k) through parameter configuration. The linear feedback shift register uses different generator polynomials (defined by tap positions) and the permutation circuit uses different permutation orders to adapt to each mode's specific requirements. This universal design eliminates the need for separate address generators for each mode, reducing overall system complexity while maintaining flexibility.
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.