OFDM Symbol Interleaver Address Generation for DVB-T 4k Mode
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Solution Overview
Problem
The existing DVB-T standard lacks an efficient symbol interleaver for the 4 k mode, which is necessary for optimizing error correction coding schemes and providing good reception for mobile users at high speeds without the need for expensive inter-carrier interference cancellation schemes.
Innovation Solution
A data processing apparatus that maps input symbols onto OFDM carrier signals using an interleaver memory and an address generator with a linear feedback shift register and permutation circuit, generating pseudo-random bit sequences and addresses to interleave symbols effectively, with a specific generator polynomial and permutation order for the 4 k mode, allowing flexible switching between 2 k, 4 k, and 8 k modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for the 4 k mode to optimize error correction coding, then error correction performance is improved, but device complexity increases due to the need for additional interleaver memory and address generation circuits
Solution Approach 1:
The address generator is designed to be mode-selectable, capable of generating addresses for 2k, 4k, and 8k modes using the same basic circuitry. The linear feedback shift register and permutation circuit can be configured with different generator polynomials and permutation orders depending on the selected mode, eliminating the need for separate address generators for each mode and reducing overall device complexity.
Solution Approach 2:
The system uses configurable parameters including the generator polynomial (e.g., g(x) = x^11 + x^9 + x^8 + x^6 + x^3 + x^2 + 1 for 4k mode), permutation order, and interleaver memory size that can be adjusted based on the selected mode. This allows a single interleaver structure to adapt to different modes by changing these parameters rather than requiring separate dedicated structures for each mode.
2Reliability
If the 2 k mode is used to provide frequent channel estimation updates for mobile applications, then reception quality for mobile users is improved, but the symbol period becomes too short to provide adequate guard periods for single frequency networks
Solution Approach 1:
The invention introduces a 4k mode with intermediate symbol period duration between 2k and 8k modes. By changing the IFFT size parameter from 2048 (2k mode) to 4096 (4k mode), the symbol period is extended to provide better guard period coverage for single frequency networks, while still being shorter than 8k mode to maintain较好的 mobile reception performance. This parameter change allows the system to find an optimal balance between these two conflicting requirements.
3Area of stationary object
If the 8 k mode is used to provide adequate guard periods for single frequency networks, then network coverage is improved, but the symbol period becomes too long to provide frequent channel estimation updates for mobile users
Solution Approach 1:
The 4k mode provides an intermediate symbol period duration that balances the conflicting requirements of network coverage and mobile reception. By selecting a moderate IFFT size of 4096, the system achieves symbol period duration that is long enough to provide adequate guard periods for single frequency networks but short enough to allow relatively frequent channel estimation updates, thus resolving the contradiction between these two requirements.
4Adaptability or versatility
If a mode-selectable address generator is implemented to support 2k, 4k, and 8k modes, then adaptability is improved, but device complexity increases due to the need for configurable parameters and control logic
Solution Approach 1:
The address generator is designed as a universal circuit that can generate addresses for all three modes (2k, 4k, and 8k) using the same basic structure. The linear feedback shift register, permutation circuit, and address check circuit work together in a unified manner, with only the generator polynomial, permutation order, and maximum address value needing to be reconfigured based on the selected mode. This universal design avoids the need for multiple separate address generators and reduces overall complexity.
Solution Approach 2:
The address generator incorporates dynamic configurability through mode selection signals that adjust the generator polynomial coefficients, permutation order, and address check limits based on the selected mode. This dynamic adaptation allows a single circuit to serve multiple purposes without requiring separate static circuits for each mode, thereby improving adaptability while controlling complexity.
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM carrier signals. The interleaver memory reads-out the data symbols on to the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, and the order being determined from a set of addresses. The set of addresses are generated from an address generator. The address generator includes a linear feedback shift register and a permutation circuit.