DVB-T2 OFDM Interleaver Using LFSR Address Permutation
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Solution Overview
Problem
The existing DVB-T and DVB-H standards lack a 0.5 k mode interleaver, which is necessary for accurate channel estimation and error correction in DVB-T2, as lower mode orders allow more frequent channel updates to track time variations due to Doppler effects, and current error correction schemes perform suboptimally with correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus that maps input symbols onto OFDM sub-carrier signals using a linear feedback shift register and permutation circuit to generate pseudo-random bit sequences and addresses, optimizing the interleaving of symbols across sub-carriers, and allowing flexible implementation across various modes by adjusting generator polynomials and permutation orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for DVB-T2 0.5 k mode, then channel estimation accuracy and error correction performance are improved, but device complexity increases due to the need for additional interleaving functionality
Solution Approach 1:
The address generator is designed to support multiple DVB-T2 modes (0.5k, 1k, 2k, 4k, 8k, 16k, 32k) through a single unified structure. By making the device universal, the patent avoids adding separate interleavers for each mode, thus improving reliability for 0.5k mode without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements mode switching by changing parameters such as the number of sub-carriers and interleaving patterns rather than adding structural complexity. The address generator adjusts its operation based on the selected mode, allowing the same hardware to provide improved channel estimation accuracy for 0.5k mode through parameter adjustment rather than structural addition.
2Ease of manufacture
If linear feedback shift register and permutation circuit are used for address generation, then implementation cost is reduced, but flexibility across different modes is limited
Solution Approach 1:
The patent employs dynamic configuration of the linear feedback shift register and permutation circuit based on the selected DVB-T2 mode. The system can switch between different generator polynomials and permutation orders, making the low-cost implementation adaptable to multiple modes (0.5k, 1k, 2k, 4k, 8k, 16k, 32k) without requiring complex hardware for each mode.
Solution Approach 2:
The patent achieves mode flexibility through parameter changes in the existing LFSR and permutation circuit structure. By adjusting the generator polynomial coefficients and permutation order based on the selected mode, the system maintains low implementation cost while supporting adaptability across all DVB-T2 modes.
3Reliability
If symbols are interleaved across sub-carriers, then error correction performance is improved, but processing time increases
Solution Approach 1:
The address generator pre-calculates and stores the interleaving pattern before actual data transmission. By performing the interleaving address generation in advance, the system improves error correction performance through proper symbol distribution across sub-carriers without adding processing time during the critical transmission phase.
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.