DVD Simulation Using Correlated Pin Groups and Time Delays
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Solution Overview
Problem
Dynamic voltage drop simulations in electrical circuits often use random signal vectors that can lead to pessimistic results due to unrealistic toggle selections, causing unnecessary modifications to the power grid and power distribution network.
Innovation Solution
The method involves identifying correlated groups of pins and assigning time delays within these groups to constrain simulations, using refined timing windows to accurately reflect switching times, and storing switching inactivity times to prevent switching during gaps, thereby reducing pessimism in dynamic voltage drop simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If purely random signal vectors are used in dynamic voltage drop simulations, then the simulation speed is fast and the approach is easy to implement, but the results become pessimistic due to unrealistic toggle selections that would be impossible to occur in actual design
Solution Approach 1:
The patent changes the parameters of signal vectors from purely random to constrained random, where the randomness is maintained for speed but additional constraints (correlation groups, timing windows, inactivity periods) are imposed to eliminate unrealistic toggles. This transforms the signal vector characteristics to achieve both speed and accuracy.
Solution Approach 2:
The patent introduces intermediary structures (correlation groups, timing windows, inactivity period constraints) that mediate between the simple random approach and the physically accurate behavior. These intermediaries filter out unrealistic toggles while preserving simulation speed.
2Ease of manufacture
If random toggle selections are used without constraints, then the simulation is simple and fast, but unnecessary modifications to the power grid and power distribution network are caused due to pessimistic results
Solution Approach 1:
The patent applies preliminary anti-action by pre-constraining the random signal vectors with correlation groups and timing windows before running the simulation. This prevents unrealistic toggles from occurring in the first place, thereby avoiding the pessimistic results that would lead to unnecessary power grid modifications.
3Measurement precision
If correlated groups and time delays are used to constrain simulations, then the accuracy of dynamic voltage drop analysis is improved, but the device complexity increases
Solution Approach 1:
The patent segments the circuit into correlation groups based on shared logic chains and timing relationships. By dividing the circuit into these segments, the complexity of constraining all signals is reduced to managing a smaller number of group-level constraints, making the system more tractable.
Solution Approach 2:
The patent performs preliminary action by pre-identifying correlation groups and calculating timing windows and inactivity periods before running the dynamic voltage drop simulation. This upfront preparation work organizes the complexity into manageable structures that can be efficiently applied during simulation.
Data Source
AI summary
Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin. The group identifier and the time delay at each pin can limit the switching activities in the DVD simulations to reduce pessimistic results from the simulations. Other methods are described, and data processing systems and machine readable media that cause such systems to perform these methods are also described.