DVFS Clock Scaling with DLL Lock Retention for Memory Interfaces
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Solution Overview
Problem
Conventional dynamic voltage and frequency scaling (DVFS) on interfaces such as memory controllers leads to loss of lock in delay-locked loops, causing corrupted memory accesses and significant dynamic power consumption, particularly in multi-processor and multi-core processor devices.
Innovation Solution
A system comprising a device power manager that supplies a scalable frequency clock and a delay-locked loop with a constant fixed frequency clock and voltage, using controlled delay line elements to generate a unique code for adjusting delays and a digital phase lock loop with glitchless multiplexers for seamless switching between clock domains, enabling efficient clock and voltage scaling and high-speed bypass modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dynamic voltage and frequency scaling is applied on an interface such as a memory controller, then power consumption is reduced, but the delay-locked loop loses its lock and memory accesses are corrupted
Solution Approach 1:
The system separates the delay-locked loop into two independent clock domains: one dedicated to the DLL operating at constant frequency/voltage to maintain lock, and another for DVFS operations. This segmentation allows power scaling without affecting DLL stability.
Solution Approach 2:
A phase interpolator is introduced as an intermediary component between the constant frequency clock and the scalable frequency interface. It enables smooth frequency transitions without causing the DLL to lose lock, thus maintaining memory access integrity while allowing power management.
2Use of energy by moving object
If conventional DVFS is applied on processors, then energy is adapted to required performance, but heavy software management is required to handle frequency transitions
Solution Approach 1:
The system implements hardware-based automatic frequency and phase adjustment mechanisms that eliminate the need for complex software management. The phase interpolator and control logic automatically handle transitions, making DVFS transparent and reducing software overhead.
3Adaptability or versatility
If multiple asynchronous clock domains are implemented with dedicated digital phase-locked loops, then various frequency requirements are met, but each DPLL generates high speed synthesized clock with significant dynamic power consumption
Solution Approach 1:
The system uses a single constant frequency clock source that serves multiple purposes: it drives the delay-locked loop and feeds the phase interpolator which then generates all required frequency variations. This eliminates the need for multiple power-hungry DPLLs while maintaining frequency adaptability.
Solution Approach 2:
The patent replaces multiple mechanical DPLL circuits with a software-controlled phase interpolator system. The interpolator uses digital signal processing to generate various frequencies from a single source, significantly reducing dynamic power consumption while maintaining the ability to match various frequency requirements.
4Adaptability or versatility
If a new synthesized frequency value is programmed on a given digital phase-locked loop in a DVFS context, then frequency scaling is achieved, but processing performance is negatively impacted during the DPLL re-lock operation
Solution Approach 1:
The phase interpolator is pre-configured with all possible phase values corresponding to different frequency requirements. When frequency scaling is needed, the system simply switches to the pre-calculated phase value without requiring re-lock operations, thus maintaining processing performance during transitions.
Data Source
AI summary
An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.