DVFS Integrated Circuit with Event Block and Performance Counters
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Solution Overview
Problem
As computing systems, such as mobile devices, increase in processing devices to improve performance, power management complexity grows, necessitating an efficient solution for dynamic voltage and frequency scaling (DVFS) that occupies less space and consumes lower power.
Innovation Solution
An integrated circuit with an event block, clock counter, performance counters, and controller, along with a DVFS governor, which monitors bus activity, counts clock signals, and calculates workload parameters to determine optimal operation frequencies and voltages for processing devices, enabling dynamic voltage and frequency scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing devices is increased to improve performance, then processing capability is improved, but power management complexity and power consumption increase
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) that allows processing devices to operate at different voltage and frequency levels based on workload demands. The system can dynamically adjust operational parameters to match actual processing needs, enabling high performance when required while consuming minimal power during low-utilization periods.
Solution Approach 2:
The system changes operational parameters (voltage and frequency) of processing devices based on monitored workload conditions. By adjusting these parameters dynamically, the system optimizes the trade-off between processing capability and power consumption, allowing multiple processing devices to coexist efficiently.
2Measurement precision
If traditional DVFS monitoring methods are used, then workload parameters can be measured, but the area occupied by monitoring circuits is large and power consumption is high
Solution Approach 1:
The patent merges the DVFS monitoring functionality directly into the existing performance counter units that are already present in the processing system. By combining these functions, the system avoids adding separate dedicated monitoring circuits, thereby reducing the additional area required while maintaining accurate workload measurement capabilities.
Solution Approach 2:
The performance counter units are designed to serve multiple functions: they simultaneously monitor workload parameters for DVFS operations and perform their original performance measurement tasks. This multi-functionality eliminates the need for dedicated monitoring hardware, reducing overall circuit area and power consumption.
Data Source
AI summary
Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.