DVFS Hardware Counting Active Memory Barriers
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Solution Overview
Problem
Current dynamic voltage and frequency scaling (DVFS) technologies in processing units, such as GPUs, introduce delays due to software-implemented decision-making and are not well-suited for GPU architectures, failing to promptly adjust voltage or frequency in response to workload changes.
Innovation Solution
Implementing DVFS hardware that counts active memory barriers within compute unit islands to dynamically adjust operating voltages and frequencies based on changes in the number of active memory barriers, allowing for real-time modifications at predetermined intervals or hybrid techniques combining dynamic and static triggering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-implemented DVFS is used, then flexibility in decision-making is improved, but response time and speed of voltage/frequency adjustment deteriorate
Solution Approach 1:
The patent introduces hardware counters as an intermediary component between the software DVFS controller and the actual voltage/frequency adjustment mechanism. These counters directly track memory barrier events and trigger voltage/frequency changes without requiring continuous software intervention, thereby maintaining software flexibility while achieving hardware-speed response times.
Solution Approach 2:
The patent replaces the software-based decision-making mechanism with a hardware-based counting and triggering mechanism. The hardware counters automatically detect memory barrier events and generate trigger signals for DVFS, substituting the slow software polling and decision-making process with fast hardware-level operations that execute at the speed of the underlying hardware events.
2Speed
If hardware DVFS counters are implemented, then response speed is improved, but device complexity increases
Solution Approach 1:
The patent leverages the existing memory barrier infrastructure already present in GPU architectures for its primary purpose of ensuring correct memory ordering. The same memory barrier events are repurposed to trigger DVFS actions, allowing the system to achieve fast hardware-level response without adding separate sensing mechanisms or increasing overall device complexity.
Solution Approach 2:
The hardware counters automatically track memory barrier events and generate trigger signals without requiring external control or complex coordination logic. The system serves itself by using its own internal memory barrier events to drive the DVFS decisions, eliminating the need for additional sensors, controllers, or complex hardware management circuits.
3Productivity
If frequent voltage/frequency adjustments are made, then performance optimization is improved, but energy overhead from adjustments increases
Solution Approach 1:
The patent implements DVFS adjustments triggered by periodic memory barrier events rather than continuous monitoring. Each memory barrier event serves as a natural periodic checkpoint where the system evaluates whether voltage/frequency changes are needed, allowing performance optimization while avoiding unnecessary adjustments between barriers and thus reducing energy overhead from frequent changes.
Data Source
AI summary
A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.