DVFS Module Frequency Control for Memory Stall Bottlenecks
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Solution Overview
Problem
In mobile devices, existing dynamic voltage and frequency scaling (DVFS) methods often result in unnecessary power consumption and performance degradation due to inadequate handling of memory stalls, as they select frequencies based on total execution time rather than actual CPU operation time, leading to inefficient operation during memory-intensive tasks.
Innovation Solution
A processor with a DVFS module that monitors microarchitecture information to hierarchically control frequencies of the CPU, cache, and memory, determining memory stall occurrences and adjusting frequencies accordingly to optimize performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing DVFS methods select frequencies based on total execution time, then frequency control is simplified, but unnecessary power consumption occurs during memory-intensive tasks
Solution Approach 1:
The patent segments the execution time into two distinct components: CPU operation time and memory stall time. The DVFS module separately measures these times using performance monitoring units, allowing independent analysis of CPU-bound and memory-bound workloads. This segmentation enables the system to avoid unnecessary frequency adjustments during memory stall periods, reducing power consumption while maintaining simple frequency control through clear temporal separation of workload types.
Solution Approach 2:
The patent implements dynamic frequency selection based on the calculated ratio of CPU operation time to total execution time. The DVFS module dynamically adjusts the CPU frequency according to workload characteristics: using a first frequency for CPU-bound tasks and a second frequency for memory-bound tasks. This dynamic adaptation resolves the contradiction by making frequency control responsive to actual workload needs rather than using a static or overly simplified approach.
2Ease of manufacture
If existing DVFS methods use total execution time for frequency selection, then implementation is straightforward, but performance degradation occurs during memory stalls
Solution Approach 1:
By segmenting execution time into CPU operation time and memory stall time, the patent enables performance-optimized frequency selection without significantly complicating implementation. The performance monitoring units automatically capture the necessary timing data, and the DVFS module uses simple ratio calculations to determine optimal frequencies. This segmentation approach maintains implementation simplicity while dramatically improving performance during memory-intensive tasks compared to using total execution time alone.
Solution Approach 2:
The patent implements a feedback mechanism where the DVFS module continuously monitors the ratio of CPU operation time to total execution time and adjusts frequencies accordingly. This feedback loop allows the system to learn workload characteristics and adapt frequency selection in real-time, improving performance during both CPU-bound and memory-bound tasks while maintaining straightforward implementation through automated monitoring and adjustment.
3Productivity
If frequency is increased to resolve memory stalls, then performance improves, but power consumption increases
Solution Approach 1:
The patent applies dynamic frequency adjustment based on the calculated ratio of CPU operation time to total execution time. When the ratio indicates CPU-bound workloads with minimal memory stalls, the system uses a higher first frequency to maximize performance. When the ratio indicates memory-bound workloads with significant stalls, the system uses a lower second frequency to conserve power, accepting that memory stall resolution will be slower. This dynamic approach resolves the contradiction by matching frequency to workload characteristics rather than universally increasing frequency.
Solution Approach 2:
The patent changes the operating frequency parameter based on workload analysis. By calculating the ratio of CPU operation time to total execution time and comparing it against threshold values, the system selectively adjusts the frequency parameter: applying a first frequency value for CPU-bound tasks and a second frequency value for memory-bound tasks. This parameter change strategy optimizes the balance between performance and power consumption by applying frequency increases only when they will actually improve performance.
Data Source
AI summary
A processor includes a central processing unit (CPU) configured to drive a dynamic voltage and frequency scaling (DVFS) module, a memory hierarchy configured to store data for an operation of the CPU, and an activity monitoring unit (AMU) configured to generate microarchitecture information by monitoring performance of the CPU or monitoring traffic of a system bus connected to the memory hierarchy. The DVFS module is configured to determine a layer within the memory hierarchy in which a memory stall occurs using the microarchitecture information, and to increase a frequency in response to the determined layer being accessed.