DVFS Operating Point Control for Fast Clock and Voltage Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing dynamic voltage and frequency scaling (DVFS) technologies face inefficiencies due to limited defined operating points, sub-optimal performance under changing application requirements, and significant overhead in switching between operating points, especially in scenarios like the Long Term Evolution (LTE) system's 'Micro Sleep' where high clock frequency is needed for short periods.
Innovation Solution
The implementation of a method that generates signals to dynamically select the most appropriate clock signal operating points and supply voltage levels based on active application use cases and current speed requirements, using a combination of software and hardwired components to optimize power consumption and reduce switching overhead, by creating a 'virtual' operating point that can adjust to meet specific use case needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a limited number of predefined OPPs are used for DVFS, then device complexity is reduced, but adaptability to different application requirements deteriorates
Solution Approach 1:
The patent implements dynamic OPP selection where the system can switch between predefined operating points based on real-time application requirements. The controller dynamically determines which OPP to activate, making the system adaptable without requiring a large number of predefined points. This resolves the contradiction by making the limited set of OPPs flexible and responsive to changing conditions.
Solution Approach 2:
The patent changes the selection of OPP parameters (clock frequency and voltage level) based on detected application requirements. By dynamically adjusting which predefined OPP is active rather than having fixed parameters, the system achieves better adaptability with a limited number of predefined operating points.
2Adaptability or versatility
If software-controlled processor is used for OPP switching, then adaptability is improved, but switching overhead increases
Solution Approach 1:
The patent replaces software-controlled processor switching with hardware-based switching mechanisms. The controller directly switches between OPPs using hardware control logic, eliminating the need for software intervention. This substitution reduces switching overhead and time loss while maintaining adaptability through hardware-based dynamic selection.
Solution Approach 2:
The patent introduces a dedicated controller as an intermediary between the application requirements and the OPP switching mechanism. This controller directly manages the switching between operating points without involving the main processor, reducing the burden on the software-controlled processor and minimizing switching overhead.
3Reliability
If highest clock frequency is used to meet real-time constraints, then reliability is improved, but energy consumption increases
Solution Approach 1:
The patent dynamically selects the appropriate clock frequency based on real-time application requirements. Instead of always using the highest frequency, the system adjusts the clock frequency to match the current workload, using higher frequencies only when necessary to meet real-time constraints. This dynamic adjustment reduces energy consumption while maintaining reliability when needed.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on detected application requirements. By adjusting the clock frequency to match the actual needs of the application rather than maintaining a fixed high frequency, the system reduces energy consumption while ensuring real-time constraints are met when necessary.
4Device complexity
If DVFS is applied with few predefined OPPs, then device complexity is reduced, but performance under changing requirements deteriorates
Solution Approach 1:
The patent implements dynamic OPP selection that allows the system to adapt to changing application requirements in real-time. The controller continuously monitors application needs and switches between the predefined OPPs accordingly, maintaining good performance despite having a limited number of predefined operating points. This dynamic behavior compensates for the limited OPP selection.
Solution Approach 2:
The patent dynamically changes which OPP is active based on application requirements. By selecting the most appropriate OPP from the predefined set based on current conditions, the system achieves better performance under changing requirements without increasing the number of predefined OPPs or the overall device complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry's present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level).