DVFS Controller with Phase Difference Measurement for Power Stability

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Solution Overview

Problem

Existing semiconductor devices for power management in portable electronic devices face challenges in achieving fast response speed and high stability due to increasing complexity and size, particularly in generating and adjusting power supply voltages efficiently.

Innovation Solution

A semiconductor device and system incorporating an open loop source generator, interface for dynamic voltage source (DVS) code output, monitoring unit for feedback, and phase difference measurement unit to set hold time in a closed loop, along with a closed loop controller for dynamic voltage and frequency scaling (DVFS), enabling accurate power management and compensation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the functionality of the power management integrated circuit is increased to improve power management capability, then the power management capability is improved, but the size and complexity of the power management integrated circuit increase

Engineering Contradiction:
Improvepower management capabilityVSAvoidsize and complexity of power management integrated circuit
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the power management system into separate functional modules: an open-loop controller for generating initial control signals, a closed-loop controller for fine-tuning based on feedback, a monitoring unit for voltage detection, and a phase difference measurement unit for timing calibration. This modular segmentation allows each unit to perform its specific function efficiently, improving overall power management capability while keeping individual module complexities manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The open-loop controller performs preliminary voltage control actions before the closed-loop controller takes over. By pre-adjusting the power supply voltage based on predicted load conditions, the system reduces the adjustment range needed by the closed-loop controller, thereby reducing response time and improving power management responsiveness without requiring excessive complexity in the feedback control path.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the hold time in the closed loop is increased to improve measurement accuracy, then the measurement accuracy is improved, but the response speed of the power management system decreases

Engineering Contradiction:
Improvephase difference measurement accuracyVSAvoidresponse speed of power management system
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent implements dynamic hold time adjustment where the hold time is not fixed but adaptively optimized based on system operating conditions. The phase difference measurement unit calibrates the hold time to match the actual propagation delay characteristics, ensuring sufficient measurement accuracy while minimizing the hold time duration. This dynamic optimization allows the system to achieve accurate measurements with the shortest necessary hold time, thereby maintaining fast response speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the hold time parameter based on measured phase differences and system performance requirements. By adjusting this critical timing parameter, the system optimizes the trade-off between measurement accuracy (which requires sufficient hold time) and response speed (which benefits from shorter hold times). This parameter optimization enables the closed-loop controller to make accurate voltage adjustments without unnecessary delay.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If the closed loop control is used to improve power supply voltage stability, then the voltage stability is improved, but the system latency increases

Engineering Contradiction:
Improvepower supply voltage stabilityVSAvoidsystem latency
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The open-loop controller performs preliminary voltage adjustment based on predicted power management requirements before the closed-loop feedback is fully processed. This pre-action reduces the magnitude of corrections needed by the closed-loop controller, thereby reducing the effective latency of the voltage stabilization process while maintaining final voltage accuracy and stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system skips unnecessary intermediate processing steps by directly calculating the required voltage adjustment based on phase difference measurements and load conditions. The closed-loop controller rapidly processes the essential feedback information and implements voltage corrections without excessive computation or waiting, thus reducing system latency while achieving stable voltage regulation through focused, efficient control actions.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS9671847B2Semiconductor device employing closed loop and open loop DVFS control and semiconductor system including the same
Publication Date: 2017.06.06 SAMSUNG ELECTRONICS CO LTD
  • US9671847B2 patent drawing
  • US9671847B2 patent drawing
  • US9671847B2 patent drawing

AI summary

In a semiconductor device for power management and a semiconductor system including the same, the semiconductor device includes an open loop source generator configured to generate an open loop source, an interface configured to output a dynamic voltage source (DVS) code based on the open loop source, a monitoring unit configured to receive a power supply voltage generated based on the DVS code as a feedback and generate a monitoring signal, and a phase difference measurement unit configured to compare the open loop source with the monitoring signal and set a hold time corresponding to an arithmetic period in a closed loop.