DVFS Power Step Controller for Processor Utilization
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Solution Overview
Problem
Conventional dynamic voltage and frequency scaling (DVFS) schemes in semiconductor devices fail to efficiently balance power consumption and performance, particularly when processor utilization approaches maximum, leading to unnecessary power consumption and thermal issues, and rely on heuristic methods that are costly and inefficient for mass production.
Innovation Solution
A method and system that perform DVFS by setting multiple power levels and steps based on processor utilization and available power, predicting future performance based on power steps rather than just performance, and adjusting operation voltage and frequency to minimize power consumption while maintaining responsiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor operates with a high frequency to improve performance, then the operation speed increases, but the power consumption increases unnecessarily
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) that allows the processor to dynamically adjust its operating frequency and voltage based on real-time workload conditions. The processor transitions between multiple power levels (first power level with first frequency and second power level with second frequency) according to utilization metrics, enabling adaptive performance optimization while minimizing unnecessary power consumption during low-utilization periods.
2Use of energy by moving object
If the operation voltage and frequency are changed to reduce power consumption, then the power efficiency improves, but the stability and performance of the system degrades
Solution Approach 1:
The patent employs a feedback mechanism that continuously monitors processor utilization and dynamically adjusts operating parameters accordingly. The DVFS controller receives utilization information, determines appropriate power levels based on predefined thresholds, and adjusts voltage and frequency to maintain system stability while optimizing power efficiency. This closed-loop control ensures that performance requirements are met while minimizing power consumption.
3Productivity
If conventional DVFS schemes are used to balance power and performance, then the operation continues, but unnecessary power consumption occurs when processor utilization approaches maximum
Solution Approach 1:
The patent introduces a power step parameter that defines the magnitude of frequency adjustment when transitioning between power levels. When processor utilization approaches maximum, the system uses the power step to predict the next appropriate frequency level, ensuring that the processor operates at the minimum necessary frequency to meet performance requirements. This parameter-based approach prevents unnecessary power consumption by avoiding over-provisioning of frequency headroom.
Data Source
AI summary
Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.