Dynamic Voltage-Frequency Scaling for Power Transient Limiting
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Solution Overview
Problem
Electronic devices are overdesigned to handle peak power transients, leading to increased size and cost due to the significant difference between thermal design power (TDP) and electronic design power (EDP) ratings, caused by current transients during processor activity.
Innovation Solution
Implementing dynamic voltage-frequency scaling (DVFS) to reduce current transients by dynamically lowering the CPU clock frequency and supply voltage during power transients, using a power-management unit (PMU) with a voltage-controlled oscillator and PID control to regulate supply voltage and clock frequency, thereby moving the electronic design power closer to the thermal design power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power-handling components are designed to handle peak current transients at higher EDP, then reliability is improved, but device size and cost increase significantly
Solution Approach 1:
The patent implements dynamic voltage-frequency scaling (DVFS) to make the processor's operating voltage and frequency adjustable in real-time. By dynamically lowering voltage and frequency during operation, the processor reduces peak current transients, allowing power-handling components to be sized for lower peak currents while maintaining reliability. This dynamic adaptation resolves the contradiction by enabling reliable operation without requiring oversized components for peak transients.
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) of the processor to reduce peak power consumption. By adjusting these parameters dynamically based on workload demands, the system achieves lower peak current transients, which allows for smaller, less expensive power-handling components while maintaining system reliability. This parameter adjustment directly addresses the contradiction between reliability and device size.
2Reliability
If power-handling components are designed to handle peak current transients at higher EDP, then reliability is improved, but device cost increases significantly
Solution Approach 1:
The patent implements dynamic voltage-frequency scaling (DVFS) to make the processor's operating voltage and frequency adjustable in real-time. By dynamically lowering voltage and frequency during operation, the processor reduces peak current transients, allowing power-handling components to be sized for lower peak currents while maintaining reliability. This dynamic adaptation resolves the contradiction by enabling reliable operation without requiring oversized components for peak transients.
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) of the processor to reduce peak power consumption. By adjusting these parameters dynamically based on workload demands, the system achieves lower peak current transients, which allows for smaller, less expensive power-handling components while maintaining system reliability. This parameter adjustment directly addresses the contradiction between reliability and device cost.
3Power
If DVFS is implemented to reduce current transients, then EDP approaches TDP reducing component overdesign, but device complexity increases
Solution Approach 1:
The patent combines the voltage control and frequency control functions into an integrated DVFS system. By merging these control mechanisms and coordinating their operation, the patent achieves effective reduction of peak current transients while avoiding the complexity of separate, independent control systems. This integration resolves the contradiction by achieving power transient reduction through a unified approach rather than multiple separate systems.
Solution Approach 2:
The patent implements feedback control mechanisms that monitor processor workload and power consumption, then adjust voltage and frequency accordingly. This feedback loop enables automatic optimization of power transients based on actual operating conditions, reducing the need for complex manual configuration or oversized components. The feedback mechanism resolves the contradiction by providing adaptive control that simplifies the overall system design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the magnitude of power transients, minimizing the need for overdesign, resulting in reduced system cost and improved packing efficiency by aligning EDP with TDP, thus enhancing the power handling capabilities of electronic devices.
Implementation Method 1
a voltage-controlled oscillator and PID control to regulate supply voltage and clock frequency
Implementation Method 2
a voltage-controlled oscillator and PID control to regulate supply voltage and clock frequency
Data Source
AI summary
A clocked electronic device includes first and second control systems. The first control system is configured to decrease clock frequency in the device in response to decreasing supply voltage. The second control system is responsive to clock lag in the device and to an amount of current drawn through the device. It is configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold.