Hardware Accelerated DVFS Register Parallel Loading
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Solution Overview
Problem
Dynamic voltage and frequency scaling in portable electronic devices often results in efficiency losses due to frequent changes in operating voltage and frequency, requiring coordination between main IC chips and external components, which is inefficiently managed by conventional serial loading of configuration settings.
Innovation Solution
A method involving multiple sets of registers and a hardware setting change accelerator that allows for parallel loading of configuration settings in response to changes in operating frequency or voltage, minimizing efficiency loss by preparing and swapping or shuffling values in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial loading of configuration settings is used to coordinate changes between main IC chip and external components, then correctness of DVFS adjustment is ensured, but efficiency is reduced due to frequent changes
Solution Approach 1:
The patent applies preliminary action by pre-loading configuration settings into a buffer register before the actual DVFS change occurs. When a DVFS event is triggered, the pre-prepared configuration values are already available in the buffer, allowing for rapid switching without serial loading delays. This resolves the contradiction by preparing data in advance (improving efficiency) while maintaining the correctness of the adjustment through proper coordination logic.
Solution Approach 2:
The patent segments the configuration setting loading process into two distinct parts: a buffer register for pre-loading configuration values and a main register set for active use. This segmentation allows the system to prepare configuration data independently in the buffer while the main system continues operation, enabling parallel preparation and switching that improves efficiency without compromising the correctness of the DVFS adjustment.
2Adaptability or versatility
If frequent changes in operating voltage and frequency are made, then power management flexibility is improved, but efficiency loss increases due to coordination overhead
Solution Approach 1:
By pre-loading configuration settings into the buffer register before DVFS events occur, the system can rapidly respond to frequent power management changes without incurring serial loading overhead each time. This preliminary preparation maintains power management flexibility for frequent adjustments while eliminating the efficiency loss that would otherwise result from repeated coordination sequences.
Solution Approach 2:
The patent creates a copy of the configuration settings in the buffer register that can be rapidly switched to without modifying the original configuration source. This copying mechanism allows frequent voltage and frequency changes to be implemented by simply switching between pre-copied configuration sets, maintaining adaptability while avoiding the efficiency loss of repeated serial loading operations.
3Productivity
If parallel loading of configuration settings is implemented, then efficiency of DVFS adjustment is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the register structure into a buffer register and main register sets, creating a dedicated preprocessing area that enables parallel loading operations. This segmentation achieves efficient parallel configuration loading while containing hardware complexity within a structured, modular register architecture rather than requiring complex distributed loading mechanisms across the entire system.
Solution Approach 2:
The buffer register acts as an intermediary structure that mediates between the configuration source and the active register sets. This intermediary enables parallel loading by providing a dedicated buffer zone where configuration values can be prepared simultaneously with system operation, achieving efficiency improvement while maintaining relatively simple hardware through the use of a single intermediary buffer structure.
Data Source
AI summary
One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.