Dynamic Voltage Frequency Scaling for Scan Shift Speed
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Solution Overview
Problem
The test time of scan tests on logic devices is dominated by shift time, which is affected by the voltage level, leading to longer test times and increased costs.
Innovation Solution
The implementation of dynamic voltage frequency scaling (DVFS) for scan shift clocks, where an internal on-die voltage source generates a regulated voltage that is maintained at a lower level during capture phases and increased to a high level during shift phases, allowing for higher shift speeds and reduced test times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher shift clock speed is used to reduce test time, then productivity is improved, but the voltage level must be increased which increases power consumption and device stress
Solution Approach 1:
The patent applies dynamic voltage frequency scaling (DVFS) to make the voltage level dynamic rather than static. The voltage is adjusted in real-time based on the operational phase: higher voltage during shift phase to enable fast shifting, and lower voltage during capture phase to reduce power consumption. This dynamic adjustment resolves the contradiction by allowing high productivity when needed while minimizing power consumption during other phases.
Solution Approach 2:
The patent implements periodic switching between different voltage levels corresponding to different test phases. The voltage alternates between high level during shift phase and low level during capture phase, creating a periodic pattern that optimizes both productivity and power consumption cycle by cycle. This periodic action allows the system to achieve high test speeds when required while reducing overall power consumption.
2Speed
If the voltage level is increased to achieve higher shift speeds, then shift time is reduced, but device stress and power consumption increase
Solution Approach 1:
The patent uses dynamic voltage adjustment to apply high voltage only during the shift phase when high speed is needed, and reduces voltage during the capture phase when high speed is not required. This dynamic approach achieves high shift speeds while minimizing device stress by limiting exposure to high voltage conditions to only when necessary for performance.
3Reliability
If scan test is performed at multiple voltage levels for thorough checking, then reliability is improved, but test time increases significantly
Solution Approach 1:
The patent implements periodic switching between high and low voltage levels during different phases of the test cycle. The high voltage is applied during shift phase for fast data loading, and low voltage during capture phase for power savings. This periodic voltage switching enables thorough testing at multiple voltage levels while significantly reducing total test time compared to performing separate tests at each voltage level.
Solution Approach 2:
The patent maintains continuous test operation by seamlessly transitioning between different voltage levels during different phases without interrupting the test flow. The high-voltage shift phase and low-voltage capture phase are continuously alternated, eliminating idle time and ensuring that useful testing action continues throughout the entire test cycle, thereby reducing total test time while maintaining comprehensive coverage.
Data Source
AI summary
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus is used for performing a scan test on a chip. In certain configurations, the apparatus includes an internal voltage source on a same die of the chip. The internal voltage source receives a constant voltage. The internal voltage source generates an internal voltage based on the constant voltage. The internal voltage is maintained at a lower voltage level in a capture phase of the scan test, and is increased from the lower voltage level to a high voltage level at a start of a shift phase of the scan test and reduced from the high voltage level to the lower voltage level at an end of the shift phase.