DVFS Circuit Synthesis via Constraint Translation
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Solution Overview
Problem
Current methods for synthesizing integrated circuits that can operate at multiple frequencies and voltage levels face challenges in efficiently determining the most stringent constraints, leading to sub-optimal results and increased complexity in achieving timing closure across various modes of operation.
Innovation Solution
A method that translates constraints across different voltage levels to a common base mode voltage, allowing for the identification of the most difficult mode to synthesize first, thereby simplifying the synthesis process and ensuring that the circuit can operate effectively across all modes by maintaining equivalent synthesis difficulty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If constraints are not translated to a common base voltage, then synthesis can be performed directly with original constraints, but it becomes difficult to identify the most stringent constraints and achieve timing closure across all modes
Solution Approach 1:
The patent introduces a base voltage as an intermediary reference point. All voltage-mode constraints are translated to equivalent constraints at this common base voltage, enabling systematic comparison and identification of the most stringent constraints without direct complex multi-voltage analysis
Solution Approach 2:
The patent transforms constraints by changing the voltage parameter to a common base voltage while adjusting frequency parameters accordingly. This parameter transformation allows constraints from different voltage modes to be expressed in a unified framework for easier analysis
2Productivity
If synthesis is performed without prioritizing the hardest-to-meet constraints, then all constraint sets can be considered equally, but iterative optimizations are required increasing synthesis time
Solution Approach 1:
The patent performs preliminary translation of all constraints to the base voltage mode before synthesis begins. This preliminary action identifies the most stringent constraints in advance, allowing the synthesis tool to prioritize these constraints from the start and avoid multiple iterative optimization cycles
Solution Approach 2:
The patent creates a feedback mechanism where translated constraints at base voltage provide information about relative difficulty of meeting constraints in different modes. This feedback guides the synthesis process to focus on the hardest-to-meet constraints first, improving overall synthesis efficiency
Data Source
AI summary
Methods and apparatus provide for automated synthesis of an integrated circuit whose voltage is varied during operation (also known as dynamic voltage and frequency scaling or DVFS). The automation may include estimating technology parameters from timing libraries, and determining a translation factor that can be used in estimating path delays for an arbitrary voltage from path delays at another voltage. The automation may also include estimating a relative difficulty to synthesize a design for meeting sets of timing constraints specified at different operating voltages and frequencies by assigning one of the constraints a common base value among all the sets, translating the other constraint to maintain equivalency of synthesis difficulty, comparing the resulting equivalent constraints to identify a hardest-to-synthesis constraint set, and using that constraint set as a goal for a first synthesis of the circuit.