DVFS Thermal Control for Semiconductor IP Clock and Voltage Scaling

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Solution Overview

Problem

Existing semiconductor devices face challenges in effectively controlling temperature fluctuations using dynamic voltage frequency scaling (DVFS), which can lead to inefficiencies in power consumption and thermal management.

Innovation Solution

The implementation of a thermal management unit (TMU) to detect temperature, a clock management unit (CMU) to generate operating clocks, a power management unit (PMU) to adjust supply voltage, and a dynamic voltage frequency scaling (DVFS) block to monitor and adjust clock and voltage levels, ensuring real-time temperature control by dynamically adjusting operating frequencies and voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If dynamic voltage frequency scaling is used to control temperature, then temperature control capability is improved, but device complexity increases

Engineering Contradiction:
Improvetemperature control capabilityVSAvoiddevice complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent implements a nested control structure where the thermal management unit detects temperature and feeds back to the DVFS block, which adjusts frequency and voltage. This nested feedback mechanism integrates temperature control within the existing DVFS framework, improving temperature control capability while managing device complexity through hierarchical control architecture.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent employs feedback control by having the thermal management unit continuously monitor temperature and provide feedback signals to the DVFS block. This feedback loop enables dynamic adjustment of operating parameters based on actual temperature conditions, achieving effective temperature control while maintaining system adaptability.

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If operating frequency and voltage are dynamically adjusted, then power consumption is reduced, but control precision requirements increase

Engineering Contradiction:
Improvepower consumptionVSAvoidcontrol precision requirements
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent replaces complex mechanical or hardware-based temperature control mechanisms with electronic control through the DVFS block. By using software-controlled frequency and voltage adjustment based on thermal management unit data, the system reduces power consumption while managing control precision requirements through digital signal processing and control algorithms.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent dynamically changes operating parameters (frequency and voltage) based on temperature conditions detected by the thermal management unit. The DVFS block adjusts these parameters in real-time to optimize power consumption while maintaining acceptable control precision through adaptive parameter tuning rather than requiring ultra-precise fixed control.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12379768B2Electronic device and method of controlling temperature associated with a semiconductor device using dynamic voltage frequency scaling (DVFS)
Publication Date: 2025.08.05 SAMSUNG ELECTRONICS CO LTD
  • US12379768B2 patent drawing
  • US12379768B2 patent drawing
  • US12379768B2 patent drawing

AI summary

An electronic device includes; an intellectual property (IP) block, a thermal management unit (TMU) that detects a temperature associated with the IP block to generate a detected temperature, a clock management unit (CMU) that generates an operating clock and provides the operating clock to the IP block, a clock generator that controls operation of the CMU in generating the operating clock, a power management unit (PMU) that generates a supply voltage provided to the CMU, and a dynamic voltage frequency scaling (DVFS) block. The DVFS block includes; a critical path monitor (CPM) that monitors the operating clock, a frequency monitor that determines a current frequency for the operating clock, a target frequency module that determines a target frequency for the operating clock, an adder that compares the target frequency and the current frequency to generate frequency comparison results, and a decide voltage module that generates deciding results in response to the frequency comparison results, wherein the PMU adjusts a level of the supply voltage in response to the deciding results.