DVFS Transition Synchronization for Shared Bus Reliability
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Solution Overview
Problem
In embedded systems, dynamic voltage and frequency scaling transitions often lead to unsynchronized hardware components, causing communication disruptions and other negative effects due to the lack of coordinated transitions among shared data buses and voltage rails.
Innovation Solution
The method involves detecting upcoming operating point transitions, identifying constraints and maximum parking latency parameters, determining the order of pausing and resuming bus activity, and simulating the transition to ensure successful synchronization, allowing or aborting the transition based on simulation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling transitions are implemented to reduce power consumption, then energy efficiency is improved, but hardware component synchronization deteriorates causing communication disruptions
Solution Approach 1:
The system performs preliminary actions by detecting upcoming operating point transitions before they occur and identifying constraints and maximum parking latency parameters in advance. This allows the system to proactively coordinate bus activity pausing and resuming sequences, ensuring hardware components remain synchronized during DVFS transitions while maintaining power efficiency benefits.
2Stability of the object's composition
If frequency and voltage transitions are coordinated within the processing unit, then transition smoothness is improved, but external hardware component synchronization deteriorates
Solution Approach 1:
The system introduces an intermediary coordination mechanism that manages bus activity pausing and resuming sequences. This intermediary layer coordinates between the processing unit's internal frequency/voltage transitions and external hardware components, ensuring both internal transition smoothness and external synchronization by acting as a mediator that orchestrates the timing and sequencing of bus operations.
3Reliability
If bus activity is paused and resumed during transitions, then hardware synchronization is improved, but transition latency increases
Solution Approach 1:
The system applies dynamics by determining optimal pausing and resuming sequences based on identified constraints and maximum parking latency parameters. Rather than using fixed timing, the system dynamically adjusts the bus activity coordination to match specific transition requirements, minimizing unnecessary pauses while ensuring proper synchronization, thus reducing overall transition latency.
4Reliability
If transition simulation is performed to ensure successful synchronization, then transition reliability is improved, but processing overhead increases
Solution Approach 1:
The system applies partial action by performing transition simulation selectively based on identified constraints and parameters, rather than simulating every possible transition scenario. This approach achieves sufficient transition reliability by simulating only the critical paths and edge cases that could cause synchronization failures, while avoiding unnecessary simulation overhead for routine transitions.
Data Source
AI summary
Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.