DVFS Operating Point Control for Low-Overhead Virtual OPP Selection
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Solution Overview
Problem
Existing dynamic voltage and frequency scaling (DVFS) technologies face inefficiencies due to sub-optimal mapping of application use cases to operating points (OPPs), leading to increased energy consumption and overhead in switching between OPPs, especially in scenarios like the LTE system's 'Micro Sleep' where high clock frequency is needed for short periods.
Innovation Solution
The implementation of a system that generates signals to dynamically select the most appropriate clock signal operating points and supply voltage levels based on active application use cases and current speed requirements, using a combination of software and hardwired components to optimize OPP selection and reduce switching overhead, effectively creating a 'virtual OPP' that adapts to varying performance needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a limited number of predefined OPPs are used, then device complexity is reduced, but power management optimality deteriorates because application use cases cannot be optimally mapped to available operating points
Solution Approach 1:
The system dynamically creates virtual OPPs by combining base OPPs with use-case-specific adjustments, allowing the operating points to adapt in real-time to application requirements rather than being fixed in advance. This resolves the contradiction by maintaining a limited set of base OPPs for simplicity while generating optimized virtual OPPs on-demand for each use case.
Solution Approach 2:
The system changes the parameters of operating points by adjusting clock frequency and voltage levels based on specific use case requirements. Instead of having many predefined OPPs, the system modifies the parameters of base OPPs to create optimized virtual OPPs for each application scenario, achieving power optimality without increasing device complexity.
2Adaptability or versatility
If software-controlled processor is used for OPP switching, then adaptability to different use cases is improved, but switching overhead increases significantly during short-duration high-frequency requirements
Solution Approach 1:
The system performs preliminary action by pre-defining base OPPs and use case profiles that specify desired performance characteristics. When a use case activates, the system quickly generates the appropriate virtual OPP by combining the base OPP with use-case-specific adjustments, avoiding time-consuming software-controlled switching while maintaining adaptability.
Solution Approach 2:
The system introduces an intermediary mechanism that combines hardware-based base OPP selection with use-case-specific parameter adjustments. This intermediary approach allows rapid switching by using hardware for the time-critical base OPP selection while applying software-based optimizations only where needed, reducing overall switching overhead.
3Reliability
If highest clock frequency is used continuously to ensure real-time performance, then reliability of meeting deadlines is improved, but energy consumption increases unnecessarily during low-performance periods
Solution Approach 1:
The system applies local quality by selecting different clock frequencies and voltage levels for different use cases and even different time periods within use cases. Instead of uniformly using the highest frequency, the system optimizes parameters locally for each specific application scenario, ensuring real-time performance where needed while reducing energy consumption during less demanding periods.
Solution Approach 2:
The system dynamically adjusts clock frequency and voltage levels based on real-time use case requirements and performance monitoring. This dynamic adaptation allows the system to maintain reliability by switching to higher frequencies when deadlines are at risk while reducing energy consumption by operating at lower frequencies during sufficient performance periods.
Data Source
AI summary
A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry's present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level).