DWA-to-Binary Converter Circuit for High-Speed Noise Reduction
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Solution Overview
Problem
High-speed data converters using DWA algorithms face challenges in converting DWA data words to binary format efficiently, leading to increased noise due to mismatched unary output elements, which affects signal-to-noise ratio and performance.
Innovation Solution
A circuit comprising a first detector to identify the start and end of logic 1 bits in a DWA data word, a logic circuit with multiplexers to select the appropriate binary value representing the number of logic 1 bits, and a second detector to handle special cases, effectively converting DWA data words to binary format.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thermometer decoder is used to convert data words, then the conversion is simple and direct, but the unary output elements are disproportionately actuated causing increased noise floor
Solution Approach 1:
The patent applies dynamic element matching by making the decoder output dynamic rather than static. The thermometer decoder is modified to dynamically select which unary output elements are actuated based on previous output states, ensuring that over time all unary elements are actuated equally despite instantaneous variations. This dynamic approach resolves the contradiction by maintaining simple decoder architecture while eliminating the disproportionate actuation that causes noise.
Solution Approach 2:
The patent implements feedback by using the previous output of the unary elements as input to control the current decoder operation. The system monitors which unary elements were actuated in the previous cycle and uses this information to adjust the current actuation pattern, ensuring balanced usage across all unary elements. This feedback mechanism eliminates the noise floor issue while preserving the simple thermometer decoder structure.
2Object-generated harmful factors
If DWA algorithm is implemented to equalize unary output element actuation, then noise floor is reduced, but the conversion complexity increases
Solution Approach 1:
The patent segments the DWA conversion process into distinct functional blocks: a thermometer decoder unit, a feedback register to store previous output states, and logic circuitry to combine current and previous states. By segmenting the complex DWA algorithm into manageable modular components, the implementation achieves noise reduction while keeping each individual component relatively simple and the overall architecture organized.
Solution Approach 2:
The patent introduces an intermediary feedback register that stores the previous output state and mediates between the simple thermometer decoder and the final output. This intermediary component enables the complex DWA functionality by providing the necessary historical context without requiring the entire complex algorithm to be implemented in a single circuit block, thus reducing overall conversion complexity.
3Speed
If high-speed conversion is achieved, then data processing speed is improved, but noise due to mismatched unary elements increases
Solution Approach 1:
The patent applies dynamic element matching that operates at high speed by using register-based feedback that can be updated at the same clock rate as the data conversion. The dynamic selection of unary elements based on previous states occurs in real-time without slowing down the conversion process, thus achieving both high speed and noise reduction simultaneously.
Solution Approach 2:
The patent maintains continuous operation by ensuring that the feedback mechanism and dynamic element selection occur in every conversion cycle without interruption. The unary elements are continuously and evenly actuated across all time periods, preventing noise accumulation while maintaining high-speed continuous data conversion operation.
Data Source
AI summary
A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.