DWDM Forwarded Clocking with ILO Jitter Filtering

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Solution Overview

Problem

High-speed data transmission systems face challenges with correlated and uncorrelated jitter, which affect the performance and reliability of transceivers, especially in dense wavelength division multiplexing (DWDM) systems, due to synchronization errors, noise, and environmental factors, making it difficult to align transmitter and receiver components effectively.

Innovation Solution

Implementing a flexible forwarded clocking mechanism in DWDM systems that allows the forwarded clock to be transmitted on any wavelength, received without excessive heating, and distributed with jitter filtering, while tracking correlated jitter to improve overall performance. This includes phase-locked loops, backchannels for communication, and injection-locked oscillators to synchronize clock distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed pairing of transmitter and receiver lanes is used, then the system is simpler to implement, but the components may become misaligned over time due to aging and environmental factors

Engineering Contradiction:
Improvelane pairing complexityVSAvoidcomponent alignment
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic lane assignment where the receiver can identify and adapt to the optimal transmitter lane for receiving the forwarded clock signal. Instead of fixed pairings, the system allows flexible assignment of clock lanes to different data lanes based on actual performance and environmental conditions, resolving the contradiction between simplicity and reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms where the receiver identifies which transmitter lane is providing the forwarded clock signal and communicates this information back. This feedback allows the system to adapt to component drift and aging by dynamically adjusting lane assignments to maintain optimal alignment between transmitter and receiver components.

Inventive Principle:
Principle #23Feedback

2Stability of the object's composition

If the forwarded clock is transmitted on a specific wavelength, then the clock signal is stable, but the receiver may require excessive heating to detect the signal

Engineering Contradiction:
Improveclock signal stabilityVSAvoidreceiver heating
Core Design Contradiction:
Stability of the object's compositionVSTemperature

Solution Approach 1:

The patent allows the forwarded clock to be transmitted on any wavelength rather than a fixed wavelength. The receiver can identify and tune to the appropriate wavelength carrying the clock signal, avoiding the need for excessive heating to detect weak signals at fixed wavelengths. This parameter flexibility resolves the contradiction between signal stability and receiver temperature requirements.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If the forwarded clock is transmitted on any wavelength, then the system is more flexible, but it becomes challenging to identify the clock lane at startup

Engineering Contradiction:
Improvewavelength flexibilityVSAvoidclock lane identification
Core Design Contradiction:
Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements preliminary identification mechanisms where the receiver attempts to identify the forwarded clock lane during startup before normal operation begins. This preliminary action allows the system to establish the correct wavelength assignment early, resolving the contradiction between wavelength flexibility and identification difficulty by addressing the identification challenge before system operation commences.

Inventive Principle:
Principle #10Preliminary action

4Device complexity

If the TIA is used to receive the clock signal, then the receiver is simpler, but uncorrelated jitter from thermal noise contaminates the forwarded clock

Engineering Contradiction:
Improvereceiver structureVSAvoidclock signal purity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent extracts the clock signal from the data signal path by using a dedicated forwarded clock lane that is separate from the data-carrying lanes. This extraction allows the clock signal to be received and processed separately, enabling the use of simpler receivers while maintaining clock purity by isolating it from the noisy data transmission path that would otherwise contaminate it with thermal noise.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution reduces uncorrelated jitter and aligns receiver lanes effectively, enhancing the reliability and performance of high-speed data transmission by minimizing timing errors and maintaining synchronization across DWDM systems.

Implementation Method 1

an injection-locked oscillator (ILO) that synchronizes to a forwarded clock from the transmitter

Methodology Applied
Scientific EffectInjection locking:

Implementation Method 2

This may include phase-locked loops, backchannels for communication, and injection-locked oscillators to synchronize clock distribution

Methodology Applied
Scientific EffectPhase-locked loop:

Data Source

PatentUS12580674B2Flexible forwarded clocking architecture for dense wavelength division multiplexing systems
Publication Date: 2026.03.17 NVIDIA CORP
  • US12580674B2 patent drawing
  • US12580674B2 patent drawing
  • US12580674B2 patent drawing

AI summary

A dense wave division multiplex (DWDM) receiver includes receiver lanes each configured to detect signals encoded in a different electromagnetic frequency band. The DWDM receiver applies a clock signal received on a variable one of the receiver lanes to lock a frequency of an injection locked oscillator (ILO) of a clock distribution network, and receiver lanes that are configured to receive data signals generate resonance on the clock distribution network. The resonant signal from the clock distribution network is applied to sample the received data signals.