Dynamic Logical-Physical Address Mapping Table Loading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In mass storage memory devices, the physical-logical address conversion table often exceeds the capacity of SRAM, leading to slower device operations due to the need to transfer portions of the table to and from flash memory, which is inefficient and costly.
Innovation Solution
A method and apparatus that send information from a host device to a mass storage memory device to initiate the loading of a portion of the logical-physical address conversion table into SRAM as a local table, based on a default logical address range, optimizing memory usage and access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the entire physical-logical address conversion table is stored in SRAM, then memory access speed is improved, but device cost increases significantly
Solution Approach 1:
The patent divides the physical-logical address conversion table into multiple segments or portions. Instead of loading the entire table into SRAM, only the currently needed portion corresponding to the active logical address range is loaded into SRAM, while other portions remain in flash memory. This segmentation approach reduces SRAM requirements and device cost while maintaining fast access for the active portion.
Solution Approach 2:
The patent pre-loads the relevant portion of the address conversion table into SRAM before it is needed for access operations. By anticipating the active logical address range and loading the corresponding table portion in advance, the system ensures fast access speed is achieved when needed, while avoiding the cost of keeping the entire table in SRAM.
2Device complexity
If only a portion of the address conversion table is kept in SRAM, then device cost is reduced, but memory access speed deteriorates due to frequent transfers between flash memory and SRAM
Solution Approach 1:
The patent implements a dynamic address range register that can be updated to reflect changes in the active logical address range. As the host system accesses different logical address ranges, the register is updated accordingly, and the SRAM is dynamically reloaded with the appropriate table portion. This dynamic adaptation ensures that the most frequently accessed data remains in SRAM, optimizing access speed while minimizing SRAM usage.
Solution Approach 2:
The system uses feedback from the host system's access patterns to determine which portion of the address conversion table should be loaded into SRAM. By monitoring the active logical address range and using this information to guide SRAM loading decisions, the system ensures that the right data is in fast memory when needed, balancing speed and cost effectively.
3Device complexity
If block mapping scheme is used to minimize conversion table size, then SRAM requirements are reduced, but mapping efficiency deteriorates for certain use cases
Solution Approach 1:
The patent applies different mapping schemes to different portions of the address conversion table based on local requirements. For the active logical address range that is currently loaded into SRAM, a more efficient page-level or fine-grained mapping scheme can be used. For inactive ranges remaining in flash memory, block mapping is sufficient. This local differentiation optimizes mapping efficiency where it matters most while keeping overall SRAM requirements manageable.
Data Source
AI summary
An apparatus includes a processor and a memory that includes computer program code. The memory and the computer program code are configured to, with the processor, cause the apparatus at least to send information from a host device to a mass storage memory device that is connected with the host device, the information including an indication of at least one default logical address range for a mass memory of the mass storage memory device. The memory and the computer program code are further configured, with the processor, to cause the apparatus, during operation of the host device with the mass storage memory device, and in response to at least one trigger condition being satisfied, to initiate a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to the at least one default logical address range. Also disclosed are corresponding methods and computer-readable storage medium, as well as a mass memory device or module that operates and is constructed in accordance with the exemplary embodiments of this invention.