Dynamic Address Mapping for Memory Latency Optimization
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Solution Overview
Problem
Modern server and client computing platforms face sub-optimal memory access performance due to static address mapping, which cannot be optimized for specific applications, leading to inefficient memory access latencies and bandwidth utilization.
Innovation Solution
A processor is configured to perform dynamic and programmable selective address decoding of physical addresses based on hint information from applications, allowing for application-specific optimization of memory access by dynamically permuting address bits, thereby improving memory access latencies and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static address mapping is used at boot time, then system stability and simplicity are maintained, but memory access performance cannot be optimized for specific applications
Solution Approach 1:
The patent implements dynamic address mapping by introducing a runtime address translation mechanism that can adaptively permute address bits based on application-specific requirements. The system transitions from static boot-time mapping to dynamic runtime mapping, allowing the address translation behavior to change adaptively during execution to optimize memory access patterns for different applications.
Solution Approach 2:
The patent changes the parameters of address mapping by introducing configurable permutation rules that can be applied to address bits at runtime. Instead of fixed mapping parameters set at boot, the system allows dynamic modification of mapping parameters (permutation rules) based on application characteristics, enabling optimization for specific workloads while maintaining system stability.
2Productivity
If application-specific dynamic address mapping is implemented, then memory access latency is reduced and bandwidth is increased, but system complexity increases
Solution Approach 1:
The patent segments the address translation process into distinct components: a virtual address translation stage, an address permutation stage, and a physical address generation stage. By dividing the address mapping function into separable segments, the system can apply complex permutation rules without overwhelming the overall system complexity, allowing performance optimization while maintaining manageable architectural complexity.
Solution Approach 2:
The patent introduces an intermediary address translation mechanism that sits between virtual address generation and physical address usage. This intermediary layer applies permutation rules to address bits without requiring fundamental changes to the underlying memory system, enabling performance optimization while isolating complexity to a dedicated translation component rather than propagating it throughout the entire system.
Data Source
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AI summary
In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.