Dynamic Address-to-Row Mapping in Skewed-Associative Cache
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Solution Overview
Problem
Conventional cache designs are vulnerable to security attacks like 'row hammer' and 'prime-and-probe,' and existing mitigation strategies, such as randomizing mappings and time-to-live-based eviction, do not provide full protection against cache attacks.
Innovation Solution
Implementing a skewed-associative cache with address-to-row mappings that can be changed dynamically without interrupting cache operations, using column and block map version bits to manage data validity and ensure secure mapping changes, while allowing processor access and minimizing performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address-to-row mapping is randomized on each boot to mitigate cache attacks, then security against cache attacks is improved, but protection is not complete and requires system restart
Solution Approach 1:
The patent implements dynamic address-to-row mapping changes during cache operation. The mapping configuration is changed from a static state to a dynamic state where mappings can be modified without system restart, enabling continuous adaptation to security threats while maintaining cache functionality.
Solution Approach 2:
The patent employs periodic changes to the address-to-row mapping configuration. By systematically changing mappings at scheduled intervals or in response to detected attacks, the system maintains security through repeated reconfiguration rather than relying on single-time randomization at boot.
2Reliability
If mapping changes are implemented during cache operation to enhance security, then continuous protection is achieved, but cache operations may be interrupted
Solution Approach 1:
The patent segments the cache into multiple independent sets or ways, allowing mapping changes to be applied to individual segments without affecting the entire cache. This enables incremental reconfiguration where some cache portions remain operational while others are being remapped, maintaining overall cache functionality during transitions.
Solution Approach 2:
The patent introduces intermediary structures such as shadow mapping tables or temporary mapping configurations that facilitate smooth transitions between mapping states. These intermediaries allow the cache to maintain valid mappings during the transition period, preventing operational interruptions while the new mapping configuration is established.
3Productivity
If dynamic mapping changes are implemented without interrupting cache operations, then system performance is maintained, but data integrity during transition must be ensured
Solution Approach 1:
The patent performs preliminary validation and preparation steps before applying mapping changes. This includes verifying the correctness of new mapping configurations, preparing backup mapping states, and ensuring data consistency checks are in place before transitioning, thereby preventing data integrity issues while maintaining performance.
Solution Approach 2:
The patent implements feedback mechanisms that monitor cache operations and data integrity during mapping transitions. By continuously checking for errors or inconsistencies and adjusting the transition process in real-time, the system ensures data integrity is maintained while minimizing performance impact through adaptive control.
Data Source
AI summary
Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.