Dynamic Address Translation via Switchable Physical Entries
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Solution Overview
Problem
In data processing systems, altering address translation information for memory remapping is typically an intrusive operation that requires halting the processor's execution or interrupting it, which negatively affects system operation, especially during development and calibration processes.
Innovation Solution
A data processing system with a memory management unit that includes an address translation table with dynamically switchable entries, allowing for non-intrusive memory remapping through a control signal that selects between multiple physical addresses corresponding to the same logical address, enabling dynamic memory mapping without halting the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address translation information is altered by traditional methods (halting processor or software remapping), then memory remapping can be achieved, but processor execution is interrupted and system operation is negatively affected
Solution Approach 1:
The patent implements dynamic address translation by providing multiple physical address fields (first physical address field and second physical address field) for each logical address entry in the address translation table. A control signal dynamically selects which physical address field is active, allowing the system to switch between different memory mappings without static reconfiguration. This dynamic approach enables memory remapping while the processor continues executing instructions, resolving the contradiction between adaptability and productivity.
2Ease of operation
If the processor is halted to permit address translation alteration, then address translation information can be modified, but system operation is interrupted
Solution Approach 1:
The patent prepares multiple physical address fields in advance within the address translation table structure. Each logical address entry contains both a first physical address field and a second physical address field, with validity bits indicating which entries are currently valid. This preliminary preparation of alternative address mappings allows the control signal to switch between mappings instantly without requiring processor halting or time-consuming reconfiguration, thus enabling easy address translation modification while minimizing execution time loss.
3Adaptability or versatility
If software remapping is used to change address translation information, then memory can be remapped, but processor execution is interrupted
Solution Approach 1:
The patent introduces a control signal as an intermediary mechanism that mediates between the address translation table and the memory mapping process. This control signal selectively enables or disables specific physical address fields based on validity bits, allowing memory remapping to occur through simple signal transitions rather than complex software intervention. The intermediary control signal enables flexible memory remapping while maintaining continuous processor execution, as the signal can be changed without interrupting the instruction stream.
Data Source
AI summary
In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.