Dynamic ALU Allocation for Vector Logic Units
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Solution Overview
Problem
In existing multi-core vector processors, each processor core has a dedicated vector arithmetic logic unit (VALU), leading to underutilization of resources due to low utilization of VALUs, especially with wide vectors, resulting in reduced performance and increased resource duplication.
Innovation Solution
Implementing a dynamic allocation system where individual ALUs of a VALU are assigned to different processor cores at each time step, allowing multiple cores to share the VALU and allocate ALUs based on Quality of Service (QoS) and time factors, enabling parallel execution of vector operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor core has a dedicated vector arithmetic logic unit (VALU), then each core can execute vector operations independently, but resource duplication increases and VALU utilization decreases
Solution Approach 1:
Multiple processor cores share a single vector arithmetic logic unit (VALU) instead of each core having its own dedicated VALU. The VALU is dynamically allocated to different cores based on workload demands, reducing resource duplication while maintaining execution capability across multiple cores.
Solution Approach 2:
The shared VALU serves multiple processor cores, functioning as a universal resource that can be dynamically assigned to any core that needs vector processing capabilities. This multi-functional approach allows one VALU to replace what would traditionally require multiple dedicated VALUs.
2Speed
If each processor core has a dedicated vector arithmetic logic unit (VALU), then each core can execute vector operations without waiting, but overall resource utilization decreases especially with wide vectors
Solution Approach 1:
The allocation of VALU resources to processor cores is dynamic rather than static. The system continuously monitors workload demands and reallocates VALU capacity to cores that currently need vector processing, ensuring both high execution speed and optimal resource utilization. This dynamic allocation allows the same VALU resources to serve different cores at different times based on instantaneous needs.
Solution Approach 2:
The shared VALU maintains continuous useful action by rapidly switching between multiple processor cores based on their current workload requirements. Instead of dedicated VALUs sitting idle when their associated core is not performing vector operations, the shared VALU continuously processes vector instructions from whichever core currently needs them, eliminating wasted processing capacity.
3Quantity of substance
If a shared vector arithmetic logic unit (VALU) is used by multiple cores, then resource duplication is reduced, but allocation complexity and coordination overhead increase
Solution Approach 1:
The system implements feedback mechanisms that monitor the workload demands of multiple processor cores and automatically adjust VALU allocation accordingly. This feedback-driven approach simplifies the allocation complexity by using automated decision-making based on real-time system state, rather than requiring complex manual or pre-configured allocation schemes.
Solution Approach 2:
Processor cores competing for shared VALU resources engage in self-service allocation through a coordination mechanism where cores indicate their vector processing needs and the system automatically assigns VALU capacity. This self-organizing approach reduces allocation complexity by allowing the system to manage itself based on observed workload patterns rather than requiring external control.
Data Source
AI summary
A method includes identifying, by a processor, one or more first arithmetic logic unit (ALU) operations in a first ALU operation queue, wherein the first ALU operations are associated with a first requested vector length and at least one first input vector; identifying, by the processor, one or more second ALU operations in a second ALU operation queue, wherein the second ALU operations are associated with a second requested vector length and at least one second input vector, wherein the processor comprises a vector logic unit, and the vector logic unit comprises a set of ALUs; determining a first subset of the set of ALUs and a second subset of the set of ALUs, in view of the first requested vector length, the second requested vector length, and one or more allocation criteria, wherein the first subset includes a first number of ALUs of the vector logic unit, and wherein the second subset includes a second number of ALUs of the vector logic unit; identifying one or more first identified operations from the first ALU operations, wherein each first identified operation corresponds to an ALU of the first subset of the set of ALUs; and performing each first identified operation using the corresponding ALU of the first subset of the set of ALUs.