Opportunistic ALU Redundancy via Dynamic Mode Switching

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Solution Overview

Problem

Current methods for increasing computational reliability, such as temporal and spatial redundancy, do not efficiently utilize available arithmetic logic units (ALUs) due to a rigid top-down approach that does not consider real-time availability, leading to underutilization and inefficiency in mission-critical operations.

Innovation Solution

A processor system that dynamically selects the redundancy mode based on the availability of ALUs, using an intermediate layer of reliability modes to opportunistically utilize underutilized ALUs for redundant execution, including mandatory, aggressive, and limited modes to optimize resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If temporal redundancy is used to increase computational reliability, then reliability is improved, but execution time and power consumption increase

Engineering Contradiction:

Improvecomputational reliabilityVSAvoidexecution time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically selects between temporal and spatial redundancy modes based on real-time ALU availability. The processor transitions from static redundancy selection to dynamic mode switching, allowing it to adapt to changing resource conditions and optimize the balance between reliability and execution efficiency.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of redundancy mode selection from fixed to variable. By introducing an intermediate layer that monitors ALU availability and adjusts the redundancy mode accordingly, the system can modify its operational parameters (temporal vs spatial redundancy) to match current resource conditions.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If spatial redundancy is used to increase computational reliability, then reliability is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improvecomputational reliabilityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Inventive Principle:

Principle #35Parameter changes

3Reliability

If rigid top-down redundancy mode selection is used, then reliability mode is determined, but ALU availability is not considered leading to underutilization

Engineering Contradiction:

Improvereliability modeVSAvoidALU utilization efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The intermediate layer continuously monitors ALU availability and uses this feedback information to dynamically adjust the redundancy mode selection. This closed-loop control ensures that reliability modes are selected based on actual resource conditions rather than predetermined configurations, optimizing both reliability and resource utilization.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

4Area of stationary object

If residual computation is used to minimize area and power consumption, then area and power are reduced, but design complexity significantly increases

Engineering Contradiction:

Improvecircuit areaVSAvoiddesign complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The intermediate layer serves multiple functions: monitoring ALU availability, determining redundancy modes, and coordinating execution. This multi-functional component avoids the need for complex residual computation circuits while achieving similar area and power savings through intelligent resource management.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10423421B2Opportunistic utilization of redundant ALU

Publication Date: 2019.09.24 INTEL CORP

AI summary

A processor includes at least one processing core that includes an operation dispatch for dispatching operations from an instruction pipeline, a plurality of arithmetic logic units for executing the operations, a plurality of multiplexers, each of which connects the operation dispatch to a respective arithmetic logic unit, and a controller configured to selectively enable at least one multiplexer to connect the operation dispatch to at least one arithmetic logic unit based on a reliability mode associated with the operation.