Elementwise Operations Hardware Accelerator with Dynamic ALU Routing
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Solution Overview
Problem
Neural networks are often expensive to implement in terms of computation, bandwidth, and power, and existing elementwise operations hardware accelerators are limited in their capabilities, restricting the types of neural networks that can be executed efficiently without external assistance.
Innovation Solution
The development of elementwise operations hardware accelerators with multiple arithmetic logic unit blocks capable of performing diverse elementwise operations in different formats, allowing for efficient execution of a varied set of neural networks without external unit assistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing elementwise operations hardware accelerators are used, then device complexity is reduced, but adaptability or versatility deteriorates
Solution Approach 1:
The patent implements a single hardware accelerator that can perform multiple elementwise operations (addition, subtraction, multiplication, division, maximum, minimum, ReLU, sigmoid, tanh, softmax) through a unified architecture. The arithmetic logic unit is designed to handle different operations by selecting appropriate computational paths, allowing one device to replace multiple specialized accelerators, thereby improving versatility without proportionally increasing complexity
Solution Approach 2:
The hardware accelerator employs dynamic operation selection through control signals that route data flow based on the required operation type. The system can dynamically switch between different arithmetic logic unit configurations and activation function implementations, enabling adaptability to various neural network requirements while maintaining a relatively stable hardware structure
2Adaptability or versatility
If multiple arithmetic logic unit blocks are added to perform diverse operations, then adaptability or versatility is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple arithmetic logic unit blocks into a shared resource pool that serves all processing pipelines. Instead of dedicating separate ALU blocks to each pipeline, the system merges ALU resources and allows dynamic allocation through an interconnection module, reducing the total number of ALU blocks needed while maintaining the capability to perform diverse operations across multiple pipelines
Solution Approach 2:
The patent introduces a temporal dimension to resource allocation by allowing arithmetic logic unit blocks to be dynamically assigned to different pipelines at different time steps. This time-multiplexed approach enables fewer ALU blocks to serve multiple pipelines sequentially, reducing hardware complexity while maintaining functional versatility across the network
3Productivity
If elementwise operations are performed simultaneously in multiple pipelines, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the interconnection module into hierarchical levels: a first interconnection module handles routing between processing pipelines and arithmetic logic units, while a second interconnection module manages data flow between other components. This segmentation of the interconnection functionality reduces the complexity of any single module while enabling simultaneous operations across multiple pipelines through coordinated routing
Data Source
AI summary
An elementwise operations hardware accelerator for use in a neural network accelerator. The elementwise operations hardware accelerator comprises one or more processing pipelines and a control module. Each processing pipeline includes: an arithmetic logic unit module comprising a plurality of different arithmetic logic unit blocks, each arithmetic logic unit block of the plurality of arithmetic logic unit blocks configured to receive one or more inputs, selectively perform one or more elementwise operations on the one or more inputs, and output a result of the one or more elementwise operations; and an interconnection module configured to receive elements of one or more input tensors and selectively provide the elements of at least one of the one or more input tensors to an arithmetic logic unit block of the plurality of arithmetic logic unit blocks as an input; The control module is configured to receive a set of commands identifying an arithmetic logic unit block of the plurality of arithmetic logic unit blocks and one or more elementwise operations to be performed by the identified arithmetic logic unit block and control the operation of the one or more processing pipelines to cause the identified arithmetic logic unit block to perform the identified one or more elementwise operations.