Dynamic Arbitration Circuit for Fair Packet Selection in Semiconductor Buffers
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Solution Overview
Problem
In semiconductor systems, existing arbitration circuits often result in unfair packet selection and processing performance degradation due to unfair arbitration determinations, particularly in multi-core networks where deadlocks and livelocks can occur, leading to reduced system velocity.
Innovation Solution
A semiconductor apparatus with an arbitration circuit that selects packets based on multiple conditions using a priority order, employing a combination of LRU and DP priority algorithms to ensure fair and sequential packet transfer, thereby mitigating unfairness and enhancing processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fair arbiter using LRU is used to sequentially transfer packets from multiple cores, then fairness and prevention of deadlocks/livelocks is improved, but processing performance and system velocity deteriorate
Solution Approach 1:
The patent applies dynamics by making the arbitration method adaptable and changeable based on system state. The controller dynamically switches between different arbitration strategies (DRR, LRU, FIFO) depending on buffer occupancy levels and traffic conditions, allowing the system to optimize between fairness and performance based on real-time requirements rather than using a fixed arbitration approach
Solution Approach 2:
The patent changes the arbitration parameter (selection method) based on buffer occupancy thresholds. When buffers are nearly full, it switches to DRR for fairness; when buffers have sufficient space, it uses FIFO for speed. This parameter change allows the system to adapt its behavior to current conditions, resolving the contradiction between fairness and performance
2Productivity
If prioritization is performed in network-on-chip with arbitration circuit, then bus-path collision is reduced, but deadlocks and livelocks occur due to unfair arbitration
Solution Approach 1:
The patent implements feedback by having the controller monitor buffer occupancy levels and adjust arbitration behavior accordingly. The controller receives feedback about buffer states from multiple cores and dynamically changes arbitration policies to prevent both deadlocks (caused by unfair arbitration) and performance degradation (caused by excessive fairness), creating a self-regulating arbitration system
Solution Approach 2:
The arbitration system transitions from static prioritization to dynamic arbitration that adapts based on real-time buffer conditions. The controller dynamically selects between DRR (for fairness when buffers are full) and FIFO (for speed when buffers have space), preventing deadlocks while maintaining high bus utilization
3Reliability
If DRR method is used to select packets based on buffer occupancy, then fairness is improved when buffers are full, but complexity of arbitration control increases
Solution Approach 1:
The patent segments the arbitration control into distinct modes (DRR mode and FIFO mode) that are activated based on buffer occupancy thresholds. This segmentation simplifies the overall control logic by dividing it into manageable, condition-based segments rather than implementing a single complex DRR system for all conditions, reducing control complexity while maintaining fairness when needed
Data Source
AI summary
A semiconductor apparatus that selects a first packet from a plurality of packets stored in a buffer and transfers the first packet. The semiconductor apparatus switches a plurality of different conditions for grouping the plurality of packets according to a priority order of the plurality of conditions; and selects the first packet from a plurality of packets pertaining to a group extracted on a condition selected by the switching according to a given selecting scheme, and transfers the first packet from the buffer.