Multi-partition Dynamic Backlight Driving Method for Flicker Reduction
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Solution Overview
Problem
In televisions using multiple-subarea dynamic backlight technology, the switching between different frame frequency standards can result in interference signals within the vertical synchronization signal, leading to a phenomenon known as backlight flicker due to duty cycle saltation areas in the PWM signal.
Innovation Solution
A method is introduced where a multiple frequency processor generates a third vertical synchronization signal by multiplying the cycle of the target signal, and then produces first and second level signals to be transmitted to a drive chip, which generates a PWM signal, thereby avoiding interference and reducing backlight flicker by ensuring the cycle of the PWM signal remains stable and synchronized with the horizontal synchronization signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the vertical synchronization signal is used directly from the scan chip without cycle adjustment, then the signal transmission is simple and fast, but interference signals appear when switching between different frame frequency standards, causing backlight flicker
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the cycle of the vertical synchronization signal before it reaches the PWM drive chip. The multiple frequency processor detects the cycle of the incoming vertical synchronization signal and adjusts it to a target cycle that is an integer multiple, preventing interference signals from appearing in the first place when frame frequency standards switch. This eliminates backlight flicker without requiring complex real-time intervention later in the signal path.
Solution Approach 2:
The patent changes the parameter of the vertical synchronization signal's cycle to resolve the contradiction. By dynamically adjusting the cycle parameter to be an integer multiple of the target cycle, the system ensures stable PWM signal generation and prevents duty cycle saltation areas. This parameter adjustment is performed by the multiple frequency processor, which modifies the signal characteristics to match the requirements of the backlight driving system.
2Reliability
If the cycle of the vertical synchronization signal is adjusted to an integer multiple target cycle, then interference signals are eliminated and backlight flicker is reduced, but additional signal processing is required
Solution Approach 1:
The patent applies universality by integrating multiple functions into the multiple frequency processor. This processor not only adjusts the cycle of the vertical synchronization signal to an integer multiple target cycle but also detects frame frequency standard switching and generates the adjusted signal. By consolidating these functions in a single processor, the system achieves stable PWM signal generation without requiring separate dedicated circuits for each function, thus managing complexity efficiently.
Solution Approach 2:
The patent implements feedback by having the multiple frequency processor detect the cycle of the incoming vertical synchronization signal and adjust it based on the detected characteristics. The processor continuously monitors the signal and modifies its cycle to maintain an integer multiple relationship with the target cycle, ensuring stable operation under varying frame frequency conditions. This feedback mechanism automatically adapts to different operating conditions without manual intervention.
Data Source
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AI summary
The embodiments of the disclosure discloses a method of driving a multiple-partition dynamic backlight and a display device. In this method, a vertical synchronization signal corresponding to an input image signal is received; a first level signal and a second level signal are outputted alternately in response to a change edge of the vertical synchronization signal, where the total duration of the first level signal and the second level signal is 1/m of the duration between the change edge and a first change edge before the change edge, wherein the change edge and the first change edge before the change edge are change edges of a same changing direction; m is a positive integer; and the drive chip receives the first level signal and the second level signal and generates a PWM signal according to the first level signal and the second level signal.