Dynamic Bandwidth Limiter for MCU-DMA Priority Inversion
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Solution Overview
Problem
In real-time systems, the activation of DMA (Direct Memory Access) can disrupt task priorities due to resource sharing with the CPU, leading to inconsistencies and reduced system execution efficiency, as higher-priority tasks are not able to fully occupy system resources efficiently.
Innovation Solution
Implementing a global bandwidth limiter (GBL) system with multiple classes that adjust the bandwidth allocation based on task priority, where the highest GBL class selected among the classes determines the system bandwidth limiter for DMA units, ensuring that critical tasks from the MCU bus are not interrupted by DMA tasks, thereby maintaining task priority order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If DMA units share bandwidth equally with MCU bus using round-robin scheduling, then resource sharing is simplified and device complexity is reduced, but task priority is violated and system execution efficiency deteriorates
Solution Approach 1:
The patent implements dynamic bandwidth allocation where the EMI arbitrator adjusts bandwidth limits for DMA units based on the priority of currently executing MCU tasks. The bandwidth limiter is dynamically modified to grant more bandwidth to DMA units when high-priority MCU tasks are running, and less bandwidth when low-priority tasks are running, making the scheduling mechanism adaptive rather than static.
Solution Approach 2:
The patent changes the bandwidth parameter allocated to DMA units based on task priority levels. By monitoring the priority of MCU tasks and adjusting the bandwidth limit parameter accordingly, the system ensures that high-priority tasks receive sufficient EMI bandwidth while still allowing DMA operations to proceed with appropriate resource sharing.
2Reliability
If DMA units are activated to off-load CPU, then CPU workload is reduced and reliability is improved, but task priority inversion occurs and system execution efficiency worsens
Solution Approach 1:
The patent introduces a bandwidth limiter as an intermediary component between the EMI arbitrator and DMA units. This mediator monitors MCU task priorities and adjusts DMA bandwidth allocation accordingly, preventing task priority inversion while maintaining the benefits of CPU off-loading through DMA operations.
Solution Approach 2:
The system implements feedback mechanisms where the execution of MCU tasks is monitored and used to dynamically adjust DMA bandwidth allocation. The EMI arbitrator receives feedback about current task priorities and modifies bandwidth limits for DMA units in real-time, ensuring that DMA operations do not interfere with high-priority MCU tasks.
3Ease of operation
If EMI arbitrator schedules requests equally by round-robin, then ease of operation is improved and scheduling is simplified, but task priority distribution is disrupted and system execution efficiency deteriorates
Solution Approach 1:
The patent transforms the static round-robin scheduling into a dynamic mechanism that adapts to task priority requirements. The bandwidth limiter is dynamically adjusted based on MCU task priority, allowing the EMI arbitrator to maintain simple round-robin operation while achieving priority-aware bandwidth distribution through parameter modification.
Data Source
AI summary
Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from a MCU (micro-controller unit) bus. A system GBL class is selected based on the highest GBL class which has been selected among the GBL classes. A bandwidth limiter of a DMA (direct memory access) unit is assigned according to the system GBL class and the priority of a second task if the DMA unit is activated by the second task. The second task is from a DMA bus, and the cycle between the DMA and MCU buses is determined according to the bandwidth limiter.