Dynamic BFEA Bin Designs for Error Correction Decoder Throughput
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Solution Overview
Problem
Existing block family error avoidance (BFEA) bin designs do not effectively address error correction decoder throughput specifications, leading to inefficient error correction and potential system performance penalties due to misalignment with read window changes over time.
Innovation Solution
Implementing BFEA bin designs that dynamically adjust the number and width of bins based on error correction decoder throughput specifications, with each bin's read window determined to maintain a threshold bit error rate, and incorporating read window overlaps to ensure comprehensive coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing BFEA bin designs are used, then device complexity is reduced, but error correction decoder throughput does not meet specifications
Solution Approach 1:
The patent implements dynamic bin designs where the number and width of bins are adjusted based on charge loss characteristics and error correction decoder throughput requirements. Instead of using fixed bin configurations, the system dynamically determines optimal bin parameters to meet throughput specifications while adapting to changing memory device conditions over time.
Solution Approach 2:
The patent changes key parameters of the bin design including the number of bins, bin widths, and read window positions. By adjusting these parameters based on charge loss measurements and throughput requirements, the system optimizes error correction decoder performance without requiring complete redesign of the bin structure.
2Reliability
If bins are made narrower to reduce read errors, then reliability improves, but the number of bins must increase causing device complexity to increase
Solution Approach 1:
The patent applies different bin widths and read window positions to different bins based on their specific charge loss characteristics. Instead of using uniform bin configurations, each bin is locally optimized with appropriate width and position to achieve the required reliability while avoiding the need to increase the total number of bins.
3Reliability
If the number of bins is increased to cover charge loss variations, then reliability improves, but device complexity and processing overhead increase
Solution Approach 1:
The system dynamically determines the optimal number of bins based on measured charge loss characteristics rather than using a fixed large number of bins. This dynamic adaptation allows the system to achieve comprehensive charge loss coverage while minimizing the number of bins required, thereby reducing management complexity.
4Productivity
If read windows are adjusted to meet throughput specifications, then productivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary characterization of charge loss characteristics during manufacturing and uses this information to pre-determine optimal read window positions and bin configurations. This preliminary action allows the system to meet throughput specifications without requiring high-precision real-time adjustments during operation.
Data Source
AI summary
A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.