Dynamic-Biased Multi-Stage Amplifier for Low-Power SC ADCs
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Solution Overview
Problem
Existing switched capacitor (SC) amplifiers in analog-to-digital converters (ADCs) have high power consumption due to the use of operational transconductance amplifiers (OTAs), which results in low power efficiency.
Innovation Solution
A multi-stage amplifier circuit with dynamic biasing, comprising a first and second multi-stage amplifier circuit, each including a second and third stage transistor, a bias transistor, and a dynamic switching circuit. The circuit samples bias voltages across capacitors in a first phase and biases the stages in a second phase, allowing for efficient amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If operational transconductance amplifiers (OTAs) are used in switched capacitor amplifiers, then amplification performance is achieved, but power consumption increases
Solution Approach 1:
The amplifier is divided into multiple stages (first stage, second stage, third stage) with each stage performing specific functions. The first stage performs initial amplification, while subsequent stages provide additional gain and buffering, allowing the system to achieve high amplification performance without relying on a single high-power OTA
Solution Approach 2:
The circuit employs periodic switching operations with defined phases (first phase for sampling, second phase for amplification) to achieve signal processing. This periodic action allows the use of lower power consumption components while maintaining amplification performance through timed operational sequences
2Use of energy by moving object
If dynamic biasing is implemented with multiple stages, then power efficiency is improved, but circuit complexity increases
Solution Approach 1:
Different biasing strategies are applied to different stages of the amplifier. The first stage uses one biasing approach optimized for its specific function, while subsequent stages use different biasing methods suited to their requirements. This localized optimization achieves overall power efficiency without requiring complex global control mechanisms
Solution Approach 2:
The circuit incorporates feedback mechanisms where the output of later stages is fed back to influence earlier stages. This feedback approach allows the multi-stage configuration to self-regulate and optimize power distribution across stages, improving power efficiency while managing complexity through natural system regulation
Data Source
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AI summary
A multi-stage amplifier circuit, comprising: a first multi-stage amplifier circuit and a second multi-stage amplifier circuit, the first multi-stage amplifier circuit including a second stage N-type transistor connected to a first stage through a 1-1-th capacitor connected to a gate of the second stage N-type transistor, a bias N-type transistor connected to a drain of the second stage N-type transistor and having a gate connected to a 1-2-th capacitor, a third stage N-type transistor having a gate connected to the drain of the second stage N-type transistor, a first current circuit configured to supply a first bias current and a second bias current, and a first dynamic switching circuit connected to the second stage N-type transistor, the bias N-type transistor, the third stage N-type transistor, and the first current circuit and configured to sample a voltage corresponding to the first bias current across the 1-1-th capacitor in a first phase and sample a voltage corresponding to the second bias current across the 1-2-th capacitor based on forming a feedback loop comprising the bias N-type and the third stage N-type transistor, and the second multi-stage amplifier circuit including a second stage P-type transistor connected to the first stage through a 2-1-th capacitor connected to a gate of the second stage P-type transistor, a bias P-type transistor connected to a drain of the second stage P-type transistor and having a gate connected to a 2-2-th capacitor, a third stage P-type transistor having a gate connected to the drain of the second stage P-type transistor, a second current circuit configured to supply the first bias current and the second bias current, and a second dynamic switching circuit connected to the second stage P-type transistor, the bias P-type transistor, the third stage P-type transistor, and the second current circuit and configured to sample a voltage corresponding to the first bias current across the 2-1-th capacitor in the first phase and sample a voltage corresponding to the second bias current across the 2-2-th capacitor based on forming a feedback loop comprising the second stage P-type transistor, the bias P-type transistor, and the third stage P-type transistor.