Dynamic Bias Circuit for Analog IC Slew Rate Optimization

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Solution Overview

Problem

Switched-capacitor circuits in analog integrated circuits face challenges with long settling times due to low slew rates, which hinder high-speed operations and increase power consumption when attempting to improve slew rates by increasing the maximum current signal.

Innovation Solution

A dynamic bias circuit that adjusts the bias voltage according to the voltage levels of input signals, using a source follower and current adjusting parts to provide variable current to the bias voltage generating part, thereby optimizing the slew rate without increasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the maximum current signal is increased to improve the slew rate, then the slew rate is improved, but the power consumption increases

Engineering Contradiction:
Improveslew rateVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The bias circuit dynamically adjusts the bias voltage based on the voltage levels of input signals. The source follower part receives input signals and generates voltages with different levels, while the current adjusting part provides variable current to the bias voltage generating part, enabling the slew rate to be optimized without continuously operating at maximum power consumption levels

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes the bias voltage parameter dynamically according to input signal conditions. When voltage difference between input signals exceeds a predetermined level, the bias voltage is adjusted to provide higher current for improved slew rate; otherwise, lower bias voltage maintains power efficiency

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the bandwidth is increased to reduce the settling time, then the settling time is reduced, but the circuit complexity increases

Engineering Contradiction:
Improvesettling timeVSAvoidcircuit complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The bias circuit uses dynamic voltage adjustment based on input signal levels to optimize settling characteristics. The source follower and current adjusting parts work together to provide variable bias conditions, achieving faster settling time without requiring complex additional circuitry for bandwidth expansion

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8610493B2Bias circuit and analog integrated circuit comprising the same
Publication Date: 2013.12.17 ELECTRONICS & TELECOMM RES INST
  • US8610493B2 patent drawing
  • US8610493B2 patent drawing
  • US8610493B2 patent drawing

AI summary

Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.