Dynamic Bias Circuit for CMOS Power Amplifier Linearity
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Solution Overview
Problem
Power amplifiers in wireless systems face challenges in achieving high power efficiency and linearity, particularly in amplifying input signal power while minimizing distortion, especially when using field-effect transistors (FETs) in CMOS technology.
Innovation Solution
The power amplifier employs a bias circuit configuration with multiple transistors and resistance elements, including a first bias circuit with transistors of the same polarity and a low-pass filter, and a second bias circuit with transistors of different polarity, to supply bias signals to the amplifying circuit, optimizing the amplification process based on input signal power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a power amplifier uses a large amount of power to amplify input signal power, then the amplification capability is improved, but the power efficiency deteriorates
Solution Approach 1:
The bias circuit dynamically adjusts the bias signal based on the input signal power level. When input signal power is high, the bias circuit increases the bias signal to maintain linearity; when input signal power is low, it reduces the bias signal to improve power efficiency. This dynamic adjustment resolves the contradiction between maintaining high amplification capability and improving power efficiency.
2Use of energy by moving object
If a power amplifier increases power efficiency, then energy consumption is reduced, but the linearity and signal distortion performance deteriorate
Solution Approach 1:
The bias circuit uses feedback from the input signal power detection to adjust the bias signal. The circuit monitors the input signal power level and automatically adjusts the bias signal accordingly - increasing bias when input power is high to maintain linearity, and decreasing bias when input power is low to maximize efficiency. This feedback mechanism resolves the contradiction between power efficiency and linearity.
3Ease of manufacture
If a power amplifier uses CMOS transistors for integration, then manufacturing cost and integrability are improved, but the power efficiency and linearity performance deteriorate
Solution Approach 1:
The invention changes the operating parameters of the CMOS transistors dynamically through the bias circuit. By adjusting the bias signal based on input power levels, the transistors operate in optimal regions that maximize both power efficiency and linearity. This parameter adjustment approach enables CMOS amplifiers to achieve performance comparable to or better than traditional designs while maintaining the manufacturing advantages of CMOS technology.
Data Source
AI summary
A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.