Dynamic-Bias Current Comparator for Nano-Power High-Speed Sensing
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Solution Overview
Problem
Conventional current comparators face a tradeoff between power consumption and speed, often requiring increased power to achieve faster response times, which is not suitable for advanced DC to DC converters and data converters.
Innovation Solution
A high-speed current comparator system with a non-linear feedback circuit and adjustable biasing circuits to limit voltage and control quiescent current, allowing for nanoampere range bias currents while minimizing internal parasitic capacitance and optimizing both power consumption and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional current comparators reduce power consumption, then power consumption decreases, but comparator speed deteriorates
Solution Approach 1:
The patent implements dynamic biasing circuits that adjust the operating point of the amplifier based on signal conditions. The bias circuits can switch between different current levels, allowing the comparator to operate at low power during idle periods and high speed during active signal processing, thus resolving the contradiction between power consumption and speed
Solution Approach 2:
The patent changes key operating parameters including bias current levels, transistor channel lengths, and feedback network configurations. By optimizing these parameters, the design achieves low power consumption in standby mode while maintaining high-speed capability when signals are present, effectively addressing the power-speed tradeoff
2Speed
If internal parasitic capacitors are charged at a faster rate to increase comparator speed, then comparator speed improves, but power consumption increases
Solution Approach 1:
The patent employs periodic switching of bias currents and use of current mirrors that activate only when needed. The biasing circuits periodically adjust their operation based on input signal detection, charging parasitic capacitors rapidly only when signal transitions occur, rather than continuously, thus achieving high speed when needed while minimizing overall power consumption
Solution Approach 2:
The patent uses preliminary detection circuits that anticipate signal transitions and pre-charge or pre-discharge parasitic capacitors in preparation for upcoming signal changes. This preliminary action reduces the actual charging time during critical transitions without requiring continuous high current, thereby improving speed while controlling power consumption
Data Source
AI summary
Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.