Dynamic Biasing in Stacked I/O Drivers for 3.3V Stress Protection
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Solution Overview
Problem
Advanced semiconductor technologies face challenges in avoiding overstress conditions for input/output (I/O) devices operating at higher voltages than their nominal tolerance, particularly in FINFET technologies where 1.5V devices need to support 3.3V signaling, leading to reliability issues like gate-oxide breakdown and hot carrier injection.
Innovation Solution
A high voltage output circuit using low voltage devices is designed with a dynamic biasing system that adjusts transistor gate voltages based on data logical values, ensuring that voltage differences across transistor terminals do not exceed the voltage tolerance, thereby preventing overstress conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 1.5V tolerant devices are used to support 3.3V signaling, then device area is reduced and manufacturing cost is lowered, but the devices experience overvoltage stress leading to reliability issues
Solution Approach 1:
The patent implements dynamic biasing circuits that adjust the gate voltages of transistors in real-time based on the operating state. The biasing voltages change dynamically between different logic states to ensure that voltage differences across transistor terminals never exceed the 1.5V tolerance, thereby preventing overstress conditions while enabling 3.3V signaling operation
Solution Approach 2:
The patent changes the biasing parameters (gate voltages) dynamically according to the operating state. By adjusting the biasing voltages based on the logic state being driven, the system maintains voltage differences within safe limits while supporting higher signaling voltages, thus improving reliability without increasing device area
2Duration of action of stationary object
If static biasing is used to protect devices from overstress, then device lifetime is extended, but the circuit complexity increases due to additional biasing circuits
Solution Approach 1:
The patent merges the biasing circuits with the existing driver circuitry by integrating the dynamic biasing functionality into the driver stage. The biasing transistors are combined with the driver transistors to form stacked configurations, reducing overall circuit complexity while maintaining protection from overstress conditions
Solution Approach 2:
The dynamic biasing circuits are controlled automatically based on the operating state without requiring external control signals. The biasing voltages are generated internally through the interaction of transistors and capacitors, allowing the circuit to self-adjust and protect itself from overstress conditions
3Reliability
If voltage differences are limited to protect low voltage devices, then device stress is reduced, but the output voltage swing is constrained
Solution Approach 1:
The patent segments the voltage protection function across multiple transistor stages in the stacked configuration. Each transistor in the stack handles a portion of the voltage swing, and the dynamic biasing ensures that individual voltage differences remain within tolerance while the cumulative output can achieve the full 3.3V signaling swing
Data Source
AI summary
A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.