Dynamic Biasing in Transconductance Amplifiers for Polarity Tracking

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Solution Overview

Problem

Existing transconductance amplifier stages experience inconsistent output polarity due to parasitic capacitances, especially during fast transients in the input voltage.

Innovation Solution

The integration of a transconductance amplifier stage with dynamic biasing circuitry and cascode circuitry, which includes transient response circuitry such as clamping circuitry, discharge circuitry, and NAT switches, to detect voltage transients and adjust bias currents accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a transconductance amplifier stage is designed to respond quickly to input voltage changes, then speed is improved, but output polarity consistency deteriorates due to parasitic capacitances

Engineering Contradiction:
Improveresponse speed to input voltage transientsVSAvoidoutput polarity consistency
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The bias current is made dynamic rather than fixed. The dynamic biasing circuitry adjusts the bias current in real-time based on the operating conditions and transient states of the amplifier, allowing the circuit to optimize its performance for both speed and polarity consistency under different conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit incorporates feedback mechanisms where the output state and transient conditions are monitored and used to adjust the bias current through the dynamic biasing circuitry. This feedback loop ensures that the amplifier maintains correct output polarity even during fast transients by adapting the bias current accordingly

Inventive Principle:
Principle #23Feedback

2Reliability

If dynamic biasing circuitry is added to maintain output polarity during transients, then output response accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveoutput polarity tracking accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dynamic biasing circuitry is designed to perform multiple functions: it provides bias current to the amplifier stage, adjusts this current dynamically during transients, and maintains output polarity consistency. By combining these functions into a single integrated circuit block, the overall complexity increase is minimized

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The dynamic biasing circuitry is merged with the transconductance amplifier stage, sharing common elements and integration structures. This consolidation reduces the total component count and interconnections compared to having separate independent circuits, thereby limiting the increase in device complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250112597A1Dynamic biasing circuitry for transconductance amplifier stage
Publication Date: 2025.04.03 TEXAS INSTRUMENTS INC
  • US20250112597A1 patent drawing
  • US20250112597A1 patent drawing
  • US20250112597A1 patent drawing

AI summary

An integrated circuit (IC) includes: first and second transistors having a respective first terminal, a respective second terminal, and a respective control terminal; and cascode circuitry having a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the cascode circuitry is coupled to the control terminal of the first transistor. The second terminal of the cascode circuitry is coupled to the control terminal of the second transistor. The third terminal of the cascode circuitry is coupled to the second terminal of the first transistor. The fourth terminal of the cascode circuitry is coupled to the second terminal of the second transistor. The IC also includes dynamic biasing circuitry having a first terminal and a second terminal. The first terminal of the dynamic biasing circuitry is coupled to the first terminals of the first and second transistors.