Dynamic Biasing for Integrated Resistor Electrical Stress Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with shallow trench isolation (STI) layers face electrical stress due to particle contamination during etching, leading to cone defects that compromise insulation and can only be detected under high electric fields, causing device failure.
Innovation Solution
Dynamic biasing of a well proximate to resistor elements adjusts based on the potential at their connection to reduce stress between the resistor elements and the well, using a configuration with a transistor and current source to limit voltage stress on the STI layer to a predetermined reliability limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic biasing is applied to mitigate electrical stress on STI layer, then device reliability is improved, but device complexity increases due to additional transistor and current source components
Solution Approach 1:
A transistor is introduced as an intermediary component between the resistor elements and the well to dynamically control the biasing. The transistor acts as a mediator that adjusts the electrical stress distribution by controlling current flow based on voltage conditions, thereby protecting the STI layer without requiring direct modification of the resistor structure
Solution Approach 2:
The biasing circuit employs feedback mechanisms where the voltage at the connection between resistor elements is sensed and used to dynamically adjust the well bias. This feedback loop ensures that the electrical stress on the STI layer is continuously monitored and regulated to remain below the breakdown threshold, improving reliability through adaptive protection
2Use of energy by moving object
If higher voltage is applied across resistor elements, then power consumption is improved, but electrical stress on STI layer increases causing insulation breakdown
Solution Approach 1:
The patent applies different voltage conditions to different regions of the device. The well region is dynamically biased to maintain lower voltage stress locally at the STI interface, while allowing higher voltage operation at the resistor elements. This local differentiation enables high power consumption without compromising insulation integrity
Solution Approach 2:
The electrical parameters (voltage and bias conditions) are dynamically changed based on operating conditions. The well bias is adjusted in real-time to ensure that even when high voltage is applied across the resistors for power-intensive operations, the voltage stress on the STI layer remains below the breakdown threshold through parameter modulation
Data Source
AI summary
In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.