Dynamic Binary Code Execution Security via Hardware Initialization Vectors
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Solution Overview
Problem
Existing solutions fail to effectively secure dynamic binary codes against fault attacks that divert the execution flow, as they rely on static binary codes with known branch instructions, and cannot handle indirect branch instructions where the branch address is determined at runtime.
Innovation Solution
A method for executing secured binary codes using a microprocessor with an arithmetic and logic unit and a hardware securing module that constructs initialization vectors from the content of destination registers, allowing for dynamic binary code execution and protection against execution flow diversion attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If indirect branch instructions are used to enable dynamic binary code execution, then adaptability is improved, but security against fault attacks deteriorates
Solution Approach 1:
The patent applies preliminary action by computing and storing initialization vectors (IVs) for all possible basic blocks before execution. The microprocessor computes an IV for each basic block based on its address and stores these in a lookup table during compilation or preprocessing. When an indirect branch instruction is executed, the IV is immediately available from the lookup table, enabling real-time authentication of the target basic block without delaying execution. This precomputation approach maintains both the adaptability of dynamic binary code execution and the security of fault attack resistance.
Solution Approach 2:
The patent introduces an intermediary mechanism - a hardware securing module that acts as a mediator between the indirect branch instruction and the executed basic block. This module intercepts the branch target address, retrieves or computes the corresponding IV, authenticates the basic block using cryptographic verification, and only allows execution if authentication succeeds. This intermediary layer enables dynamic execution while preventing fault attacks by verifying integrity before execution.
2Reliability
If initialization vectors are computed at runtime for indirect branches, then security is improved, but processing time increases
Solution Approach 1:
The patent eliminates runtime computation overhead by performing the initialization vector computation in advance. During compilation or preprocessing, IVs for all basic blocks are computed based on their addresses and stored in a lookup table in memory. At runtime, when an indirect branch is executed, the IV is simply retrieved from the lookup table using the basic block address as an index, requiring only a memory access rather than cryptographic computation. This precomputation strategy maintains security while avoiding execution time penalties.
3Reliability
If fault detection mechanisms are added to secured binary code, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the fault detection functionality directly into the existing indirect branch instruction execution mechanism. The hardware securing module that already exists for managing initialization vectors and authentication is enhanced to perform cryptographic verification of basic blocks. Rather than adding separate fault detection hardware, the authentication logic is integrated into the branch execution path, utilizing the same hardware resources for both control flow management and security verification. This merging approach improves reliability without proportionally increasing device complexity.
Data Source
AI summary
A method for executing a binary code including the execution of an indirect load instruction which provokes the reading of a data line associated with an address obtained from the content of a destination register, then the construction of an initialization vector from the content of this data line, then the loading of this constructed initialization vector in a microprocessor, then the execution of an indirect branch instruction which provokes a branch directly to a first encrypted instruction line of a following basic block whose address is obtained from the content of the same destination register, then the decryption of the cryptogram of each encrypted instruction line of the following basic block using the initialization vector loaded in the microprocessor.