Iterative Error Correction With Dynamic Bit Flipping Order
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Solution Overview
Problem
Bit Flipping (BF) decoders in memory subsystems suffer from lower error correction capability compared to MinSum Algorithm (MSA)-based decoders, leading to false flips and increased codeword error rates, which hinders their deployment in energy-conscious applications.
Innovation Solution
Implementing a dynamic bit flipping order for iterative error correction, where the error corrector modifies the bit flipping order between iterations based on parity checks and channel information, switching between forward and backward orders to reduce false flips and improve error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Bit Flipping (BF) decoders are used for error correction, then energy consumption is reduced, but error correction capability deteriorates leading to false flips and increased codeword error rates
Solution Approach 1:
The patent applies dynamics by making the bit flipping order adaptive and changeable during iterative decoding. Instead of using a fixed flipping order, the system dynamically adjusts the order based on channel information and parity check results from previous iterations, allowing the decoder to adapt to the specific error patterns encountered and improve reliability while maintaining energy efficiency
Solution Approach 2:
The patent changes the parameter of bit flipping order from static to dynamic. By modifying the flipping order based on channel state information and iteration progress, the system optimizes the decoding process to reduce false flips and improve error correction capability without sacrificing the energy efficiency that makes BF decoders attractive
2Device complexity
If a fixed bit flipping order is used in iterative error correction, then device complexity is reduced, but false flips increase and error correction capability deteriorates
Solution Approach 1:
The system transitions from a static bit flipping order to a dynamic one that adapts during iterative decoding. The flipping order is adjusted based on channel information and parity check outcomes, enabling the decoder to respond to actual error patterns and reduce false flips without requiring complex additional hardware
3Reliability
If dynamic bit flipping order is implemented, then error correction capability improves approaching MSA-based decoders, but device complexity increases
Solution Approach 1:
The patent modifies the bit flipping order parameter dynamically based on channel state information and iteration progress. This parameter change enables the decoder to achieve error correction performance接近 to MSA-based decoders by adapting to error patterns, while the implementation remains relatively simple by leveraging existing channel information rather than requiring complex additional mechanisms
Data Source
AI summary
Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.